source: FPGA/FAD/FACT_FAD_TB_lib/hdl/adc_controller_beha.vhd@ 228

--
-- VHDL Architecture FACT_FAD_TB_lib.adc_controller.beha
--
-- Created:
--          by - Benjamin Krumm.UNKNOWN (EEPC8)
--          at - 13:46:10 25.03.2010
--
-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY adc_controller IS
   PORT( 
      adc_oeb : OUT    STD_LOGIC 
   );

-- Declarations

END adc_controller ;

ARCHITECTURE beha OF adc_controller IS
BEGIN
  
  start_adc_proc: process
  begin
    adc_oeb <= '1';
    wait for 1 us;
    wait for 10 ns;
    adc_oeb <= '0';
    wait;
  end process start_adc_proc;
  
END ARCHITECTURE beha;