source: FPGA/FAD/FACT_FAD_TB_lib/hdl/clock_generator.vhd@ 228

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:40:20 01/07/2010 
-- Design Name: 
-- Module Name:    clock_generator - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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-- hds interface_start
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--  synthesis translate_off
entity clock_generator is
   generic( 
      clock_period : time := 20 ns;
      reset_time   : time := 50 ns
   );
   port( 
      clk : out    STD_LOGIC  := '0';
      rst : out    STD_LOGIC  := '0'
   );

-- Declarations

end clock_generator ;
-- hds interface_end

architecture Behavioral of clock_generator is

begin
 
        clock_gen_proc: process
        begin
                clk <= '0';
                wait for clock_period / 2;
                clk <= '1';
                wait for clock_period / 2;
        end process clock_gen_proc;
        
        reset_gen_proc: process
        begin
                rst <= '1';
                wait for reset_time;
                rst <= '0';
                wait;
        end process reset_gen_proc;


end Behavioral;
--synthesis translate_on