source: FPGA/FAD/FACT_FAD_TB_lib/hdl/w5300_emulator_beha.vhd@ 228

--
-- VHDL Architecture FACT_FAD_TB_lib.w5300_emulator.beha
--
-- Created:
--          by - FPGA_Developer.UNKNOWN (EEPC8)
--          at - 07:51:36 04.02.2010
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY FACT_FAD_lib;
USE FACT_FAD_lib.fad_definitions.all;

entity w5300_emulator is
  port(
    addr : in std_logic_vector(9 downto 0);
    data : inout std_logic_vector(15 downto 0);
    rd : in std_logic;
    wr : in std_logic
  );
end entity w5300_emulator;

architecture beha of w5300_emulator is

  signal open_done : std_logic_vector(7 downto 0) := (others => '0');
  signal data_temp : std_logic_vector(15 downto 0);
  
  signal RSR_0, RSR_1  : std_logic_vector (15 downto 0);
  signal FIFOR_CNT : integer := 0;
  
begin
  
  data <= data_temp when (rd = '0') else (others => 'Z');
  data_temp <= data when (wr = '0') else (others => 'Z');
  
  set_proc : process
  begin
    RSR_0 <= X"0000";
    RSR_1 <= X"0000";
    wait for 250 us;
    RSR_1 <= X"0001";
    wait for 2 ms;
    RSR_1 <= X"0002";
    wait;
  end process set_proc;

  w5300_proc : process (addr)
  begin
    for i in 0 to 7 loop
      if (addr = conv_integer(W5300_S0_SSR) + i * 64) then
        if (open_done(i) = '0') then
          data_temp <= X"0013";
          open_done(i) <= '1';
        else
          data_temp <= X"0017";
        end if;
      elsif (addr = conv_integer(W5300_S0_TX_FSR) + i * conv_integer(W5300_S_INC)) then
        data_temp <= X"0000";
      elsif (addr = conv_integer(W5300_S0_TX_FSR + 2) + i * conv_integer(W5300_S_INC)) then
        data_temp <= X"3C00";
      elsif (addr = conv_integer(W5300_S0_RX_RSR)) then
        data_temp <= RSR_0;
      elsif (addr = conv_integer(W5300_S0_RX_RSR) + 2) then
        data_temp <= RSR_1;
      elsif (addr = conv_integer(W5300_S0_RX_FIFOR)) then
        if (FIFOR_CNT = 0) then
          data_temp <= X"A000";
          FIFOR_CNT <= 1;
        elsif (FIFOR_CNT = 1) then
          data_temp <= X"0500";
          FIFOR_CNT <= 2;
        elsif (FIFOR_CNT = 2) then
          data_temp <= X"0000";
        end if;
      else
        null;
      end if;
    end loop;
  end process w5300_proc;

  
end architecture beha;