source: FPGA/FAD/FACT_FAD_lib/hdl/DCM_25MHz_38nsPS_BEHAVIORAL.vhd@ 228

Last change on this file since 228 was 215, checked in by dneise, 14 years ago
initial commit (2nd part): only VHDL and UCF files were commited.
  • Property svn:executable set to *
File size: 6.5 KB
Line 
1-- Coregen VHDL wrapper file modified by HDL Designer
2
3--------------------------------------------------------------------------------
4-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
5--------------------------------------------------------------------------------
6-- ____ ____
7-- / /\/ /
8-- /___/ \ / Vendor: Xilinx
9-- \ \ \/ Version : 10.1.03
10-- \ \ Application : xaw2vhdl
11-- / / Filename : DCM_25MHz_38nsPS.vhd
12-- /___/ /\ Timestamp : 03/29/2010 10:34:42
13-- \ \ / \
14-- \___\/\___\
15--
16--Command: xaw2vhdl-st C:\DOKUME~1\FPGA_D~1\LOKALE~1\Temp\coregen_FPGA_Developer\coregen\project\DCM_25MHz_38nsPS.xaw C:\DOKUME~1\FPGA_D~1\LOKALE~1\Temp\coregen_FPGA_Developer\coregen\project\DCM_25MHz_38nsPS
17--Design Name: DCM_25MHz_38nsPS
18--Device: xc3s700a-4fg484
19--
20-- Module DCM_25MHz_38nsPS
21-- Written for synthesis tool: Precision
22
23library ieee;
24use ieee.std_logic_1164.ALL;
25use ieee.numeric_std.ALL;
26library UNISIM;
27use UNISIM.Vcomponents.ALL;
28
29entity DCM_25MHz_38nsPS is
30 port ( CLKIN_IN : in std_logic;
31 RST_IN : in std_logic;
32 CLKIN_IBUFG_OUT : out std_logic;
33 CLK0_OUT : out std_logic;
34 LOCKED_OUT : out std_logic);
35end DCM_25MHz_38nsPS;
36
37architecture BEHAVIORAL of DCM_25MHz_38nsPS is
38
39-- hds translate_off
40
41 attribute CLK_FEEDBACK : string ;
42 attribute CLKDV_DIVIDE : string ;
43 attribute CLKFX_DIVIDE : string ;
44 attribute CLKFX_MULTIPLY : string ;
45 attribute CLKIN_DIVIDE_BY_2 : string ;
46 attribute CLKIN_PERIOD : string ;
47 attribute CLKOUT_PHASE_SHIFT : string ;
48 attribute DESKEW_ADJUST : string ;
49 attribute DFS_FREQUENCY_MODE : string ;
50 attribute DLL_FREQUENCY_MODE : string ;
51 attribute DUTY_CYCLE_CORRECTION : string ;
52 attribute FACTORY_JF : string ;
53 attribute PHASE_SHIFT : string ;
54 attribute STARTUP_WAIT : string ;
55 signal CLKFB_IN : std_logic;
56 signal CLKIN_IBUFG : std_logic;
57 signal CLK0_BUF : std_logic;
58 signal GND_BIT : std_logic;
59 component IBUFG
60 port ( I : in std_logic;
61 O : out std_logic);
62 end component;
63
64 component BUFG
65 port ( I : in std_logic;
66 O : out std_logic);
67 end component;
68
69 component DCM_SP
70 -- synthesis translate_off
71 generic( CLK_FEEDBACK : string := "1X";
72 CLKDV_DIVIDE : real := 2.0;
73 CLKFX_DIVIDE : integer := 1;
74 CLKFX_MULTIPLY : integer := 4;
75 CLKIN_DIVIDE_BY_2 : boolean := FALSE;
76 CLKIN_PERIOD : real := 10.0;
77 CLKOUT_PHASE_SHIFT : string := "NONE";
78 DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
79 DFS_FREQUENCY_MODE : string := "LOW";
80 DLL_FREQUENCY_MODE : string := "LOW";
81 DUTY_CYCLE_CORRECTION : boolean := TRUE;
82 FACTORY_JF : bit_vector := x"C080";
83 PHASE_SHIFT : integer := 0;
84 STARTUP_WAIT : boolean := FALSE;
85 DSS_MODE : string := "NONE");
86 -- synthesis translate_on
87 port ( CLKIN : in std_logic;
88 CLKFB : in std_logic;
89 RST : in std_logic;
90 PSEN : in std_logic;
91 PSINCDEC : in std_logic;
92 PSCLK : in std_logic;
93 DSSEN : in std_logic;
94 CLK0 : out std_logic;
95 CLK90 : out std_logic;
96 CLK180 : out std_logic;
97 CLK270 : out std_logic;
98 CLKDV : out std_logic;
99 CLK2X : out std_logic;
100 CLK2X180 : out std_logic;
101 CLKFX : out std_logic;
102 CLKFX180 : out std_logic;
103 STATUS : out std_logic_vector (7 downto 0);
104 LOCKED : out std_logic;
105 PSDONE : out std_logic);
106 end component;
107
108 attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
109 attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
110 attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1";
111 attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4";
112 attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
113 attribute CLKIN_PERIOD of DCM_SP_INST : label is "40.000";
114 attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED";
115 attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
116 attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
117 attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
118 attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
119 attribute FACTORY_JF of DCM_SP_INST : label is "C080";
120 attribute PHASE_SHIFT of DCM_SP_INST : label is "243";
121 attribute STARTUP_WAIT of DCM_SP_INST : label is "FALSE";
122
123-- hds translate_on
124
125begin
126
127-- hds translate_off
128
129 GND_BIT <= '0';
130 CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
131 CLK0_OUT <= CLKFB_IN;
132 CLKIN_IBUFG_INST : IBUFG
133 port map (I=>CLKIN_IN,
134 O=>CLKIN_IBUFG);
135
136 CLK0_BUFG_INST : BUFG
137 port map (I=>CLK0_BUF,
138 O=>CLKFB_IN);
139
140 DCM_SP_INST : DCM_SP
141 -- synthesis translate_off
142 generic map( CLK_FEEDBACK => "1X",
143 CLKDV_DIVIDE => 2.0,
144 CLKFX_DIVIDE => 1,
145 CLKFX_MULTIPLY => 4,
146 CLKIN_DIVIDE_BY_2 => FALSE,
147 CLKIN_PERIOD => 40.000,
148 CLKOUT_PHASE_SHIFT => "FIXED",
149 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
150 DFS_FREQUENCY_MODE => "LOW",
151 DLL_FREQUENCY_MODE => "LOW",
152 DUTY_CYCLE_CORRECTION => TRUE,
153 FACTORY_JF => x"C080",
154 PHASE_SHIFT => 243,
155 STARTUP_WAIT => FALSE)
156 -- synthesis translate_on
157 port map (CLKFB=>CLKFB_IN,
158 CLKIN=>CLKIN_IBUFG,
159 DSSEN=>GND_BIT,
160 PSCLK=>GND_BIT,
161 PSEN=>GND_BIT,
162 PSINCDEC=>GND_BIT,
163 RST=>RST_IN,
164 CLKDV=>open,
165 CLKFX=>open,
166 CLKFX180=>open,
167 CLK0=>CLK0_BUF,
168 CLK2X=>open,
169 CLK2X180=>open,
170 CLK90=>open,
171 CLK180=>open,
172 CLK270=>open,
173 LOCKED=>LOCKED_OUT,
174 PSDONE=>open,
175 STATUS=>open);
176
177
178-- hds translate_on
179
180end BEHAVIORAL;
181
182
183
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