source: FPGA/FAD/FACT_FAD_lib/hdl/clock_generator_struct.vhd@ 222

-- VHDL Entity FACT_FAD_lib.clock_generator.symbol
--
-- Created:
--          by - kai.UNKNOWN (E5PCXX)
--          at - 12:09:56 04.05.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY clock_generator IS
   PORT( 
      CLK       : IN     std_logic;
      CLK_25    : OUT    std_logic;
      CLK_25_PS : OUT    std_logic;
      CLK_50    : OUT    std_logic
   );

-- Declarations

END clock_generator ;

--
-- VHDL Architecture FACT_FAD_lib.clock_generator.struct
--
-- Created:
--          by - kai.UNKNOWN (E5PCXX)
--          at - 12:09:56 04.05.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.all;

LIBRARY FACT_FAD_lib;

ARCHITECTURE struct OF clock_generator IS

   -- Architecture declarations

   -- Internal signal declarations

   -- Implicit buffer signal declarations
   SIGNAL CLK_25_internal : std_logic;


   -- Component Declarations
   COMPONENT dcm_50_to_25
   PORT (
      CLKIN_IN        : IN     std_logic;
      CLK0_OUT        : OUT    std_logic;
      CLKFX_OUT       : OUT    std_logic;
      CLKIN_IBUFG_OUT : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT dcm_ps_38ns
   PORT (
      CLKIN_IN : IN     std_logic;
      CLK0_OUT : OUT    std_logic
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : dcm_50_to_25 USE ENTITY FACT_FAD_lib.dcm_50_to_25;
   FOR ALL : dcm_ps_38ns USE ENTITY FACT_FAD_lib.dcm_ps_38ns;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : dcm_50_to_25
      PORT MAP (
         CLKIN_IN        => CLK,
         CLKFX_OUT       => CLK_25_internal,
         CLKIN_IBUFG_OUT => OPEN,
         CLK0_OUT        => CLK_50
      );
   U_1 : dcm_ps_38ns
      PORT MAP (
         CLKIN_IN => CLK_25_internal,
         CLK0_OUT => CLK_25_PS
      );

   -- Implicit buffered output assignments
   CLK_25 <= CLK_25_internal;

END struct;