source: FPGA/FAD/FACT_FAD_lib/hdl/data_generator.vhd@ 228

Last change on this file since 228 was 215, checked in by dneise, 14 years ago
initial commit (2nd part): only VHDL and UCF files were commited.
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Line 
1--
2-- VHDL Architecture FACT_FAD_lib.data_generator.beha
3--
4-- Created:
5-- by - FPGA_Developer.UNKNOWN (EEPC8)
6-- at - 14:36:14 10.02.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
9
10library IEEE;
11use IEEE.STD_LOGIC_1164.ALL;
12use IEEE.STD_LOGIC_ARITH.ALL;
13use IEEE.STD_LOGIC_UNSIGNED.ALL;
14library fact_fad_lib;
15use fact_fad_lib.fad_definitions.all;
16
17-- -- Uncomment the following library declaration if instantiating
18-- -- any Xilinx primitives in this code.
19-- library UNISIM;
20-- use UNISIM.VComponents.all;
21
22entity data_generator is
23 port(
24 clk : in std_logic;
25 data_out : out std_logic_vector (63 downto 0);
26 addr_out : out std_logic_vector (11 downto 0);
27 write_ea : out std_logic_vector (0 downto 0) := "0";
28 ram_start_addr : in std_logic_vector (11 downto 0);
29 ram_write_ea : in std_logic;
30 ram_write_ready : out std_logic := '0';
31 config_start_mm, config_start_cm, config_start_spi : out std_logic := '0';
32 config_ready_mm, config_ready_cm, config_ready_spi : in std_logic;
33 config_started_mm, config_started_cm, config_started_spi : in std_logic;
34 roi_array : in roi_array_type;
35 roi_max : in roi_max_type;
36 sensor_array : in sensor_array_type;
37 sensor_ready : in std_logic;
38 dac_array : in dac_array_type;
39 package_length : in std_logic_vector (15 downto 0);
40 board_id : in std_logic_vector (3 downto 0);
41 crate_id : in std_logic_vector (1 downto 0);
42 trigger_id : in std_logic_vector (47 downto 0);
43 trigger : in std_logic;
44 s_trigger : in std_logic;
45 new_config : in std_logic;
46 config_started : out std_logic := '0';
47 adc_data_array : in adc_data_array_type;
48 adc_oeb : out std_logic := '1';
49 adc_otr : in std_logic_vector (3 downto 0);
50 drs_channel_id : out std_logic_vector (3 downto 0) := (others => '0');
51 drs_dwrite : out std_logic := '1';
52 drs_clk_en, drs_read_s_cell : out std_logic := '0';
53 drs_read_s_cell_ready : in std_logic;
54 drs_s_cell_array : in drs_s_cell_array_type
55 );
56end data_generator ;
57
58architecture Behavioral of data_generator is
59
60type state_generate_type is (INIT, CONFIG, CONFIG1, CONFIG2,CONFIG3, CONFIG4, WRITE_HEADER, WRITE_EXTERNAL_TRIGGER, WRITE_INTERNAL_TRIGGER, WRITE_BOARD_ID, WRITE_TEMPERATURES,
61 WRITE_DAC1, WRITE_DAC2, WRITE_CHANNEL_ID, WRITE_START_CELL, WRITE_ROI, WRITE_ADC_DATA, WRITE_DATA_END, WRITE_DATA_END_WAIT,
62 WRITE_END_FLAG, WRITE_DATA_STOP,
63 WRITE_DATA_IDLE, WAIT_FOR_ADC, WAIT_FOR_STOP_CELL, START_DRS_READING);
64
65signal state_generate : state_generate_type := INIT;
66signal start_addr : std_logic_vector (11 downto 0) := (others => '0');
67
68signal data_cntr : integer range 0 to 1024 := 0;
69signal evnt_cntr : std_logic_vector (31 downto 0) := (others => '0');
70signal addr_cntr : integer range 0 to RAM_SIZE_64B := 0; -- counts 64 bit words
71signal channel_id : integer range 0 to 9 := 0;
72signal adc_wait_cnt : integer range 0 to 7 := 0;
73
74
75begin
76
77
78 generate_data : process (clk)
79 begin
80 if rising_edge (clk) then
81
82 addr_out <= start_addr + conv_std_logic_vector(addr_cntr, 12);
83
84 case state_generate is
85 when INIT =>
86 state_generate <= CONFIG;
87
88 when CONFIG =>
89 config_started <= '1';
90 -- config config manager
91 config_start_cm <= '1';
92 if (config_started_cm = '1') then
93 state_generate <= CONFIG1;
94 end if;
95 when CONFIG1 =>
96 if (config_ready_cm = '1') then
97 config_started <= '0';
98 config_start_cm <= '0';
99 config_start_mm <= '1';
100 end if;
101 if (config_started_mm = '1') then
102 state_generate <= CONFIG2;
103 end if;
104 when CONFIG2 =>
105 if (config_ready_mm = '1') then
106 config_start_mm <= '0';
107 config_start_spi <= '1';
108 end if;
109 if (config_started_spi = '1') then
110 state_generate <= CONFIG3;
111 end if;
112 when CONFIG3 =>
113 if (config_ready_spi = '1') then
114 config_start_spi <= '0';
115 state_generate <= WRITE_DATA_IDLE;
116 end if;
117
118 when WRITE_DATA_IDLE =>
119 if (new_config = '1') then
120 state_generate <= CONFIG;
121 end if;
122 if (ram_write_ea = '1' and (trigger = '1' or s_trigger = '1')) then
123 -- stop drs, dwrite low
124 drs_dwrite <= '0';
125 -- start reading of drs stop cell
126 drs_read_s_cell <= '1';
127 -- enable adc output
128 adc_oeb <= '0';
129 start_addr <= ram_start_addr;
130 state_generate <= WRITE_HEADER;
131 evnt_cntr <= evnt_cntr + 1;
132 end if;
133 when WRITE_HEADER =>
134 write_ea <= "1";
135 data_out <= X"0000" & PACKAGE_VERSION & PACKAGE_SUB_VERSION & package_length & X"FB01";
136 addr_cntr <= addr_cntr + 3;
137 state_generate <= WRITE_BOARD_ID;
138 when WRITE_BOARD_ID => -- crate ID & board ID
139 data_out <= (63 downto 10 => '0') & crate_id & "1000" & board_id;
140 addr_cntr <= addr_cntr + 1;
141 state_generate <= WRITE_TEMPERATURES;
142 when WRITE_TEMPERATURES => -- temperatures
143 if (sensor_ready = '1') then
144 data_out <= conv_std_logic_vector (sensor_array (3), 16)
145 & conv_std_logic_vector (sensor_array (2), 16)
146 & conv_std_logic_vector (sensor_array (1), 16)
147 & conv_std_logic_vector (sensor_array (0), 16);
148 addr_cntr <= addr_cntr + 1;
149 state_generate <= WRITE_DAC1;
150 end if;
151
152 when WRITE_DAC1 =>
153 data_out <= conv_std_logic_vector (dac_array (3), 16)
154 & conv_std_logic_vector (dac_array (2), 16)
155 & conv_std_logic_vector (dac_array (1), 16)
156 & conv_std_logic_vector (dac_array (0), 16);
157 addr_cntr <= addr_cntr + 1;
158 state_generate <= WRITE_DAC2;
159 when WRITE_DAC2 =>
160 data_out <= conv_std_logic_vector (dac_array (7), 16)
161 & conv_std_logic_vector (dac_array (6), 16)
162 & conv_std_logic_vector (dac_array (5), 16)
163 & conv_std_logic_vector (dac_array (4), 16);
164 addr_cntr <= addr_cntr + 1;
165 state_generate <= WAIT_FOR_STOP_CELL;
166
167 when WAIT_FOR_STOP_CELL =>
168 drs_read_s_cell <= '0';
169 if (drs_read_s_cell_ready = '1') then
170 state_generate <= START_DRS_READING;
171 end if;
172
173 when START_DRS_READING =>
174 --drs channel number
175 drs_channel_id <= conv_std_logic_vector (channel_id, 4);
176 --starte drs-clocking
177 --adc_oeb <= '0'; -- nur für Emulator
178 drs_clk_en <= '1';
179 adc_wait_cnt <= 0;
180 state_generate <= WRITE_CHANNEL_ID;
181
182 when WRITE_CHANNEL_ID => -- write DRS and Channel IDs
183 data_out <= conv_std_logic_vector(0,10) & conv_std_logic_vector(3,2) & conv_std_logic_vector(channel_id,4)
184 & conv_std_logic_vector(0,10) & conv_std_logic_vector(2,2) & conv_std_logic_vector(channel_id,4)
185 & conv_std_logic_vector(0,10) & conv_std_logic_vector(1,2) & conv_std_logic_vector(channel_id,4)
186 & conv_std_logic_vector(0,10) & conv_std_logic_vector(0,2) & conv_std_logic_vector(channel_id,4);
187 addr_cntr <= addr_cntr + 1;
188 state_generate <= WRITE_START_CELL;
189 when WRITE_START_CELL => -- write start cells
190 data_out <= "000000" & drs_s_cell_array (3)
191 & "000000" & drs_s_cell_array (2)
192 & "000000" & drs_s_cell_array (1)
193 & "000000" & drs_s_cell_array (0);
194 addr_cntr <= addr_cntr + 1;
195 state_generate <= WRITE_ROI;
196 when WRITE_ROI => -- write ROI
197 data_out <= "00000" & conv_std_logic_vector (roi_array((3) * 9 + channel_id), 11)
198 & "00000" & conv_std_logic_vector (roi_array((2) * 9 + channel_id), 11)
199 & "00000" & conv_std_logic_vector (roi_array((1) * 9 + channel_id), 11)
200 & "00000" & conv_std_logic_vector (roi_array((0) * 9 + channel_id), 11);
201 addr_cntr <= addr_cntr + 1;
202 state_generate <= WAIT_FOR_ADC;
203 when WAIT_FOR_ADC =>
204 -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
205 if (adc_wait_cnt < (4 + 3)) then -- anpassen!!!! -- 3 für Simulation, 4 für FPGA???
206 adc_wait_cnt <= adc_wait_cnt + 1;
207 else
208 state_generate <= WRITE_ADC_DATA;
209 end if;
210 when WRITE_ADC_DATA =>
211 if (data_cntr < roi_max (channel_id)) then
212 data_out <= "000" & adc_otr(3) & adc_data_array(3)
213 & "000" & adc_otr(2) & adc_data_array(2)
214 & "000" & adc_otr(1) & adc_data_array(1)
215 & "000" & adc_otr(0) & adc_data_array(0);
216 addr_cntr <= addr_cntr + 1;
217 state_generate <= WRITE_ADC_DATA;
218 data_cntr <= data_cntr + 1;
219 else
220 drs_clk_en <= '0';
221 --adc_oeb <= '1'; -- nur für Emulator
222 if (channel_id = 8) then
223 state_generate <= WRITE_EXTERNAL_TRIGGER;
224 adc_oeb <= '1';
225 else
226 channel_id <= channel_id + 1; -- increment channel_id
227 state_generate <= START_DRS_READING;
228 data_cntr <= 0;
229 end if;
230 end if;
231
232
233 when WRITE_EXTERNAL_TRIGGER => -- external trigger ID
234 addr_out <= start_addr + conv_std_logic_vector(1, 12);
235 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & trigger_id(15 downto 0) & trigger_id(31 downto 16);
236 state_generate <= WRITE_INTERNAL_TRIGGER;
237 when WRITE_INTERNAL_TRIGGER => -- internal trigger ID
238 addr_out <= start_addr + conv_std_logic_vector(2, 12);
239 data_out <= X"0000" & trigger_id(39 downto 32) & trigger_id(47 downto 40) & evnt_cntr(15 downto 0) & evnt_cntr(31 downto 16);
240 state_generate <= WRITE_END_FLAG;
241 when WRITE_END_FLAG =>
242 data_out <= (63 downto 32 => '0') & X"04FE" & X"4242";
243 addr_cntr <= addr_cntr + 1;
244 state_generate <= WRITE_DATA_END;
245 when WRITE_DATA_END =>
246 write_ea <= "0";
247 ram_write_ready <= '1';
248 state_generate <= WRITE_DATA_END_WAIT;
249 when WRITE_DATA_END_WAIT =>
250 state_generate <= WRITE_DATA_STOP;
251 when WRITE_DATA_STOP =>
252 drs_dwrite <= '1';
253 data_cntr <= 0;
254 addr_cntr <= 0;
255 channel_id <= 0;
256 ram_write_ready <= '0';
257 state_generate <= WRITE_DATA_IDLE;
258
259 when others =>
260 null;
261
262 end case; -- state_generate
263 end if; -- rising_edge (clk)
264 end process generate_data;
265
266end Behavioral;
267
268
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