source: FPGA/FAD/FACT_FAD_lib/hdl/fad_board_struct.vhd@ 228

Last change on this file since 228 was 215, checked in by dneise, 14 years ago
initial commit (2nd part): only VHDL and UCF files were commited.
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1-- VHDL Entity FACT_FAD_lib.FAD_Board.symbol
2--
3-- Created:
4-- by - kai.UNKNOWN (E5PCXX)
5-- at - 15:27:37 19.05.2010
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY FAD_Board IS
14 PORT(
15 A0_D : IN std_logic_vector (11 DOWNTO 0);
16 A1_D : IN std_logic_vector (11 DOWNTO 0);
17 A2_D : IN std_logic_vector (11 DOWNTO 0);
18 A3_D : IN std_logic_vector (11 DOWNTO 0);
19 A_OTR : IN std_logic_vector (3 DOWNTO 0);
20 D0_SROUT : IN std_logic;
21 D1_SROUT : IN std_logic;
22 D2_SROUT : IN std_logic;
23 D3_SROUT : IN std_logic;
24 TRG : IN STD_LOGIC;
25 W_INT : IN std_logic;
26 X_50M : IN STD_LOGIC;
27 A_CLK : OUT std_logic_vector (3 DOWNTO 0);
28 D0_SRCLK : OUT STD_LOGIC;
29 D1_SRCLK : OUT STD_LOGIC;
30 D2_SRCLK : OUT STD_LOGIC;
31 D3_SRCLK : OUT STD_LOGIC;
32 DAC_CS : OUT std_logic;
33 DENABLE : OUT std_logic;
34 DWRITE : OUT std_logic := '1';
35 D_A : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
36 EE_CS : OUT std_logic;
37 LED_0 : OUT std_logic;
38 LED_2 : OUT std_logic;
39 LED_3 : OUT std_logic;
40 MOSI : OUT std_logic := '0';
41 OE_ADC : OUT STD_LOGIC;
42 RS485_C_DE : OUT std_logic;
43 RS485_C_RE : OUT std_logic;
44 RS485_E_DE : OUT std_logic;
45 RS485_E_RE : OUT std_logic;
46 RSRLOAD : OUT std_logic := '0';
47 SRIN : OUT std_logic;
48 S_CLK : OUT std_logic;
49 T0_CS : OUT std_logic;
50 T1_CS : OUT std_logic;
51 T2_CS : OUT std_logic;
52 T3_CS : OUT std_logic;
53 TRG_V : OUT std_logic;
54 W_A : OUT std_logic_vector (9 DOWNTO 0);
55 W_CS : OUT std_logic := '1';
56 W_RD : OUT std_logic := '1';
57 W_RES : OUT std_logic := '1';
58 W_WR : OUT std_logic := '1';
59 MISO : INOUT std_logic;
60 W_D : INOUT std_logic_vector (15 DOWNTO 0)
61 );
62
63-- Declarations
64
65END FAD_Board ;
66
67--
68-- VHDL Architecture FACT_FAD_lib.FAD_Board.struct
69--
70-- Created:
71-- by - kai.UNKNOWN (E5PCXX)
72-- at - 15:27:37 19.05.2010
73--
74-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
75--
76LIBRARY ieee;
77USE ieee.std_logic_1164.all;
78USE ieee.std_logic_arith.all;
79USE IEEE.NUMERIC_STD.all;
80
81LIBRARY FACT_FAD_lib;
82USE FACT_FAD_lib.fad_definitions.all;
83LIBRARY FACT_FAD_test_devices_lib;
84USE FACT_FAD_test_devices_lib.drs4_pack.all;
85USE ieee.std_logic_unsigned.all;
86
87LIBRARY FACT_FAD_lib;
88
89ARCHITECTURE struct OF FAD_Board IS
90
91 -- Architecture declarations
92
93 -- Internal signal declarations
94 SIGNAL CLK_25_PS : std_logic;
95 SIGNAL CLK_50 : std_logic;
96 SIGNAL SRCLK : std_logic := '0';
97 SIGNAL adc_data_array : adc_data_array_type;
98 SIGNAL board_id : std_logic_vector(3 DOWNTO 0);
99 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);
100 SIGNAL led : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
101 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);
102
103
104 -- Component Declarations
105 COMPONENT FAD_main
106 PORT (
107 CLK : IN std_logic ;
108 SROUT_in_0 : IN std_logic ;
109 SROUT_in_1 : IN std_logic ;
110 SROUT_in_2 : IN std_logic ;
111 SROUT_in_3 : IN std_logic ;
112 adc_data_array : IN adc_data_array_type ;
113 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
114 board_id : IN std_logic_vector (3 DOWNTO 0);
115 crate_id : IN std_logic_vector (1 DOWNTO 0);
116 trigger : IN std_logic ;
117 wiz_int : IN std_logic ;
118 CLK_25_PS : OUT std_logic ;
119 CLK_50 : OUT std_logic ;
120 RSRLOAD : OUT std_logic := '0';
121 SRCLK : OUT std_logic := '0';
122 adc_oeb : OUT std_logic := '1';
123 dac_cs : OUT std_logic ;
124 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
125 drs_dwrite : OUT std_logic := '1';
126 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
127 mosi : OUT std_logic := '0';
128 sclk : OUT std_logic ;
129 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
130 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
131 wiz_cs : OUT std_logic := '1';
132 wiz_rd : OUT std_logic := '1';
133 wiz_reset : OUT std_logic := '1';
134 wiz_wr : OUT std_logic := '1';
135 sio : INOUT std_logic ;
136 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
137 );
138 END COMPONENT;
139
140 -- Optional embedded configurations
141 -- pragma synthesis_off
142 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
143 -- pragma synthesis_on
144
145
146BEGIN
147 -- Architecture concurrent statements
148 -- HDL Embedded Text Block 1 eb_ID
149 -- hard-wired IDs
150 board_id <= "0101";
151 crate_id <= "01";
152
153 -- HDL Embedded Text Block 2 ADC_CLK
154 -- ADC_CLK 2
155 A_CLK (0) <= CLK_25_PS;
156 A_CLK (1) <= CLK_25_PS;
157 A_CLK (2) <= CLK_25_PS;
158 A_CLK (3) <= CLK_25_PS;
159
160 -- HDL Embedded Text Block 3 ADC_DATA
161 -- ADC_DATA 3
162 adc_data_array (0) <= A0_D;
163 adc_data_array (1) <= A1_D;
164 adc_data_array (2) <= A2_D;
165 adc_data_array (3) <= A3_D;
166
167 -- HDL Embedded Text Block 4 SRCLK
168 -- SRCLK 4
169 D0_SRCLK <= SRCLK;
170 D1_SRCLK <= SRCLK;
171 D2_SRCLK <= SRCLK;
172 D3_SRCLK <= SRCLK;
173
174 -- HDL Embedded Text Block 5 T_CS
175 -- T_CS 5
176 T0_CS <= sensor_cs (0);
177 T1_CS <= sensor_cs (1);
178 T2_CS <= sensor_cs (2);
179 T3_CS <= sensor_cs (3);
180
181 -- HDL Embedded Text Block 6 MISC
182 -- MISC 6
183 TRG_V <= '0';
184 RS485_C_RE <= '1';
185 RS485_C_DE <= '0';
186 RS485_E_RE <= '1';
187 RS485_E_DE <= '0';
188 DENABLE <= '1';
189 SRIN <= 'Z';
190 EE_CS <= '1';
191 LED_0 <= 'Z';
192 LED_2 <= 'Z';
193 LED_3 <= 'Z';
194
195
196
197 -- Instance port mappings.
198 I_testboard_main : FAD_main
199 PORT MAP (
200 CLK => X_50M,
201 SROUT_in_0 => D0_SROUT,
202 SROUT_in_1 => D1_SROUT,
203 SROUT_in_2 => D2_SROUT,
204 SROUT_in_3 => D3_SROUT,
205 adc_data_array => adc_data_array,
206 adc_otr_array => A_OTR,
207 board_id => board_id,
208 crate_id => crate_id,
209 trigger => TRG,
210 wiz_int => W_INT,
211 CLK_25_PS => CLK_25_PS,
212 CLK_50 => CLK_50,
213 RSRLOAD => RSRLOAD,
214 SRCLK => SRCLK,
215 adc_oeb => OE_ADC,
216 dac_cs => DAC_CS,
217 drs_channel_id => D_A,
218 drs_dwrite => DWRITE,
219 led => led,
220 mosi => MOSI,
221 sclk => S_CLK,
222 sensor_cs => sensor_cs,
223 wiz_addr => W_A,
224 wiz_cs => W_CS,
225 wiz_rd => W_RD,
226 wiz_reset => W_RES,
227 wiz_wr => W_WR,
228 sio => MISO,
229 wiz_data => W_D
230 );
231
232END struct;
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