source: FPGA/FAD/FACT_FAD_lib/hdl/fad_main.ucf@ 228

Last change on this file since 228 was 215, checked in by dneise, 14 years ago
initial commit (2nd part): only VHDL and UCF files were commited.
  • Property svn:executable set to *
File size: 4.3 KB
Line 
1Net clk LOC = E12 | IOSTANDARD=LVCMOS33;
2
3
4## Net reset LOC = R13 | IOSTANDARD=LVCMOS33 | PULLDOWN;
5
6Net wiz_reset LOC = H19 | IOSTANDARD=LVCMOS33;
7Net wiz_cs LOC = J18 | IOSTANDARD=LVCMOS33;
8Net wiz_wr LOC = K18 | IOSTANDARD=LVCMOS33;
9Net wiz_rd LOC = K17 | IOSTANDARD=LVCMOS33;
10Net wiz_int LOC = K19 | IOSTANDARD=LVCMOS33;
11
12## Net trigger CLOCK_DEDICATED_ROUTE = FALSE;
13Net trigger LOC = R13 | IOSTANDARD=LVCMOS33 | PULLDOWN;
14
15Net wiz_addr<0> LOC = B20 | IOSTANDARD=LVCMOS33;
16Net wiz_addr<1> LOC = A20 | IOSTANDARD=LVCMOS33;
17Net wiz_addr<2> LOC = C19 | IOSTANDARD=LVCMOS33;
18Net wiz_addr<3> LOC = B19 | IOSTANDARD=LVCMOS33;
19Net wiz_addr<4> LOC = D19 | IOSTANDARD=LVCMOS33;
20Net wiz_addr<5> LOC = A19 | IOSTANDARD=LVCMOS33;
21Net wiz_addr<6> LOC = D18 | IOSTANDARD=LVCMOS33;
22Net wiz_addr<7> LOC = C18 | IOSTANDARD=LVCMOS33;
23Net wiz_addr<8> LOC = E17 | IOSTANDARD=LVCMOS33;
24Net wiz_addr<9> LOC = A18 | IOSTANDARD=LVCMOS33;
25
26Net wiz_data<0> LOC = B17 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
27Net wiz_data<1> LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
28Net wiz_data<2> LOC = A17 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
29Net wiz_data<3> LOC = D21 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
30Net wiz_data<4> LOC = A16 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
31Net wiz_data<5> LOC = D22 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
32Net wiz_data<6> LOC = A15 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
33Net wiz_data<7> LOC = E22 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
34Net wiz_data<8> LOC = B15 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
35Net wiz_data<9> LOC = F18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
36Net wiz_data<10> LOC = A14 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
37Net wiz_data<11> LOC = F19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
38Net wiz_data<12> LOC = B13 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
39Net wiz_data<13> LOC = F20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
40Net wiz_data<14> LOC = A13 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
41Net wiz_data<15> LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW | DRIVE = 8;
42
43NET led<7> LOC = W21 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
44NET led<6> LOC = Y22 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
45NET led<5> LOC = V20 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
46NET led<4> LOC = V19 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
47NET led<3> LOC = U19 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
48NET led<2> LOC = U20 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
49NET led<1> LOC = T19 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
50NET led<0> LOC = R20 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
51
52NET rsrload LOC = B4 | IOSTANDARD = LVCMOS33;
53NET srclk LOC = A4 | IOSTANDARD = LVCMOS33;
54NET clk_50 LOC = B6 | IOSTANDARD = LVCMOS33;
55NET clk_25_ps LOC = A5 | IOSTANDARD = LVCMOS33;
56
57##NET "RX_CLK_N" LOC = "A11" | IOSTANDARD = LVCMOS33 ;
58##NET "RX_CLK_P" LOC = "A12" | IOSTANDARD = LVCMOS33 ;
59#NET dbg_cntr<19> LOC = "B4" | IOSTANDARD = LVCMOS33 ;
60#NET dbg_cntr<18> LOC = "A4" | IOSTANDARD = LVCMOS33 ;
61#NET dbg_cntr<17> LOC = "A5" | IOSTANDARD = LVCMOS33 ;
62#NET dbg_cntr<16> LOC = "B6" | IOSTANDARD = LVCMOS33 ;
63#NET dbg_cntr<15> LOC = "A6" | IOSTANDARD = LVCMOS33 ;
64#NET dbg_cntr<14> LOC = "A7" | IOSTANDARD = LVCMOS33 ;
65#NET dbg_cntr<13> LOC = "A8" | IOSTANDARD = LVCMOS33 ;
66#NET dbg_cntr<12> LOC = "A9" | IOSTANDARD = LVCMOS33 ;
67#NET dbg_cntr<11> LOC = "C10" | IOSTANDARD = LVCMOS33 ;
68#NET dbg_cntr<10> LOC = "A10" | IOSTANDARD = LVCMOS33 ;
69##NET "TX_CLK_N" LOC = "AB10" | IOSTANDARD = LVCMOS33 ;
70##NET "TX_CLK_P" LOC = "AA10" | IOSTANDARD = LVCMOS33 ;
71#NET dbg_cntr<9> LOC = "AA3" | IOSTANDARD = LVCMOS33 ;
72#NET dbg_cntr<8> LOC = "AB2" | IOSTANDARD = LVCMOS33 ;
73#NET dbg_cntr<7> LOC = "AA4" | IOSTANDARD = LVCMOS33 ;
74#NET dbg_cntr<6> LOC = "AB3" | IOSTANDARD = LVCMOS33 ;
75#NET dbg_cntr<5> LOC = "AB6" | IOSTANDARD = LVCMOS33 ;
76#NET dbg_cntr<4> LOC = "AA6" | IOSTANDARD = LVCMOS33 ;
77#NET dbg_cntr<3> LOC = "AB7" | IOSTANDARD = LVCMOS33 ;
78#NET dbg_cntr<2> LOC = "Y7" | IOSTANDARD = LVCMOS33 ;
79#NET dbg_cntr<1> LOC = "AB8" | IOSTANDARD = LVCMOS33 ;
80#NET dbg_cntr<0> LOC = "AA8" | IOSTANDARD = LVCMOS33 ;
81#
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