source: FPGA/FAD/FACT_FAD_lib/hdl/fad_main_struct.vhd@ 222

Last change on this file since 222 was 215, checked in by dneise, 16 years ago
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1-- VHDL Entity FACT_FAD_lib.FAD_main.symbol
2--
3-- Created:
4-- by - kai.UNKNOWN (E5PCXX)
5-- at - 15:27:35 19.05.2010
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12LIBRARY FACT_FAD_lib;
13USE FACT_FAD_lib.fad_definitions.all;
14
15ENTITY FAD_main IS
16 PORT(
17 CLK : IN std_logic;
18 SROUT_in_0 : IN std_logic;
19 SROUT_in_1 : IN std_logic;
20 SROUT_in_2 : IN std_logic;
21 SROUT_in_3 : IN std_logic;
22 adc_data_array : IN adc_data_array_type;
23 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
24 board_id : IN std_logic_vector (3 DOWNTO 0);
25 crate_id : IN std_logic_vector (1 DOWNTO 0);
26 trigger : IN std_logic;
27 wiz_int : IN std_logic;
28 CLK_25_PS : OUT std_logic;
29 CLK_50 : OUT std_logic;
30 RSRLOAD : OUT std_logic := '0';
31 SRCLK : OUT std_logic := '0';
32 adc_oeb : OUT std_logic := '1';
33 dac_cs : OUT std_logic;
34 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
35 drs_dwrite : OUT std_logic := '1';
36 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
37 mosi : OUT std_logic := '0';
38 sclk : OUT std_logic;
39 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
40 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
41 wiz_cs : OUT std_logic := '1';
42 wiz_rd : OUT std_logic := '1';
43 wiz_reset : OUT std_logic := '1';
44 wiz_wr : OUT std_logic := '1';
45 sio : INOUT std_logic;
46 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
47 );
48
49-- Declarations
50
51END FAD_main ;
52
53--
54-- VHDL Architecture FACT_FAD_lib.FAD_main.struct
55--
56-- Created:
57-- by - kai.UNKNOWN (E5PCXX)
58-- at - 15:27:36 19.05.2010
59--
60-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
61--
62library ieee;
63use ieee.std_logic_1164.all;
64use IEEE.STD_LOGIC_ARITH.all;
65use ieee.STD_LOGIC_UNSIGNED.all;
66
67library fact_fad_lib;
68use fact_fad_lib.fad_definitions.all;
69
70library UNISIM;
71use UNISIM.VComponents.all;
72USE IEEE.NUMERIC_STD.all;
73USE IEEE.std_logic_signed.all;
74
75LIBRARY FACT_FAD_lib;
76LIBRARY FACT_FAD_TB_lib;
77
78ARCHITECTURE struct OF FAD_main IS
79
80 -- Architecture declarations
81
82 -- Internal signal declarations
83 SIGNAL CLK_25 : std_logic;
84 SIGNAL adc_data_array_int : adc_data_array_type;
85 SIGNAL adc_otr : std_logic_vector(3 DOWNTO 0);
86 SIGNAL addr_out : std_logic_vector(11 DOWNTO 0);
87 SIGNAL config_addr : std_logic_vector(7 DOWNTO 0);
88 SIGNAL config_busy : std_logic;
89 SIGNAL config_data : std_logic_vector(15 DOWNTO 0);
90 SIGNAL config_data_valid : std_logic;
91 SIGNAL config_rd_en : std_logic;
92 SIGNAL config_ready : std_logic;
93 SIGNAL config_ready_cm : std_logic;
94 SIGNAL config_ready_spi : std_logic;
95 SIGNAL config_start : std_logic := '0';
96 SIGNAL config_start_cm : std_logic;
97 SIGNAL config_start_spi : std_logic := '0';
98 SIGNAL config_started : std_logic;
99 SIGNAL config_started_cu : std_logic := '0';
100 SIGNAL config_started_mm : std_logic;
101 SIGNAL config_started_spi : std_logic := '0';
102 SIGNAL config_wr_en : std_logic;
103 SIGNAL dac_array : dac_array_type;
104 SIGNAL data_out : std_logic_vector(63 DOWNTO 0);
105 SIGNAL drs_clk_en : std_logic := '0';
106 SIGNAL drs_read_s_cell : std_logic := '0';
107 SIGNAL drs_read_s_cell_ready : std_logic;
108 SIGNAL drs_s_cell_array : drs_s_cell_array_type;
109 SIGNAL new_config : std_logic := '0';
110 SIGNAL package_length : std_logic_vector(15 DOWNTO 0);
111 SIGNAL ram_addr : std_logic_vector(13 DOWNTO 0);
112 SIGNAL ram_data : std_logic_vector(15 DOWNTO 0);
113 SIGNAL ram_start_addr : std_logic_vector(11 DOWNTO 0);
114 SIGNAL ram_write_ea : std_logic;
115 SIGNAL ram_write_ready : std_logic := '0';
116 SIGNAL roi_array : roi_array_type;
117 SIGNAL roi_max : roi_max_type;
118 SIGNAL s_trigger : std_logic := '0';
119 SIGNAL sensor_array : sensor_array_type;
120 SIGNAL sensor_ready : std_logic;
121 SIGNAL trigger_id : std_logic_vector(47 DOWNTO 0);
122 SIGNAL wiz_busy : std_logic;
123 SIGNAL wiz_number_of_channels : std_logic_vector(3 DOWNTO 0) := (others => '0');
124 SIGNAL wiz_ram_start_addr : std_logic_vector(13 DOWNTO 0) := (others => '0');
125 SIGNAL wiz_write_ea : std_logic := '0';
126 SIGNAL wiz_write_end : std_logic := '0';
127 SIGNAL wiz_write_header : std_logic := '0';
128 SIGNAL wiz_write_length : std_logic_vector(16 DOWNTO 0) := (others => '0');
129 SIGNAL write_ea : std_logic_vector(0 DOWNTO 0) := "0";
130
131 -- Implicit buffer signal declarations
132 SIGNAL CLK_25_PS_internal : std_logic;
133 SIGNAL CLK_50_internal : std_logic;
134
135
136 -- Component Declarations
137 COMPONENT adc_buffer
138 PORT (
139 adc_data_array : IN adc_data_array_type;
140 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
141 clk_ps : IN std_logic;
142 adc_data_array_int : OUT adc_data_array_type;
143 adc_otr : OUT std_logic_vector (3 DOWNTO 0)
144 );
145 END COMPONENT;
146 COMPONENT clock_generator
147 PORT (
148 CLK : IN std_logic ;
149 CLK_25 : OUT std_logic ;
150 CLK_25_PS : OUT std_logic ;
151 CLK_50 : OUT std_logic
152 );
153 END COMPONENT;
154 COMPONENT control_unit
155 PORT (
156 clk : IN STD_LOGIC ;
157 config_addr : IN std_logic_vector (7 DOWNTO 0);
158 config_rd_en : IN std_logic ;
159 config_start : IN std_logic ;
160 config_wr_en : IN std_logic ;
161 config_busy : OUT std_logic ;
162 config_data_valid : OUT std_logic ;
163 config_ready : OUT std_logic ;
164 config_started : OUT std_logic := '0';
165 dac_array : OUT dac_array_type ;
166 roi_array : OUT roi_array_type ;
167 config_data : INOUT std_logic_vector (15 DOWNTO 0)
168 );
169 END COMPONENT;
170 COMPONENT dataRAM_64bit_16bit
171 PORT (
172 clka : IN std_logic ;
173 dina : IN std_logic_VECTOR (63 DOWNTO 0);
174 addra : IN std_logic_VECTOR (11 DOWNTO 0);
175 wea : IN std_logic_VECTOR (0 DOWNTO 0);
176 clkb : IN std_logic ;
177 addrb : IN std_logic_VECTOR (13 DOWNTO 0);
178 doutb : OUT std_logic_VECTOR (15 DOWNTO 0)
179 );
180 END COMPONENT;
181 COMPONENT data_generator
182 PORT (
183 clk : IN std_logic ;
184 data_out : OUT std_logic_vector (63 DOWNTO 0);
185 addr_out : OUT std_logic_vector (11 DOWNTO 0);
186 write_ea : OUT std_logic_vector (0 DOWNTO 0) := "0";
187 ram_start_addr : IN std_logic_vector (11 DOWNTO 0);
188 ram_write_ea : IN std_logic ;
189 ram_write_ready : OUT std_logic := '0';
190 config_start_mm : OUT std_logic := '0';
191 config_start_cm : OUT std_logic := '0';
192 config_start_spi : OUT std_logic := '0';
193 config_ready_mm : IN std_logic ;
194 config_ready_cm : IN std_logic ;
195 config_ready_spi : IN std_logic ;
196 config_started_mm : IN std_logic ;
197 config_started_cm : IN std_logic ;
198 config_started_spi : IN std_logic ;
199 roi_array : IN roi_array_type ;
200 roi_max : IN roi_max_type ;
201 sensor_array : IN sensor_array_type ;
202 sensor_ready : IN std_logic ;
203 dac_array : IN dac_array_type ;
204 package_length : IN std_logic_vector (15 DOWNTO 0);
205 board_id : IN std_logic_vector (3 DOWNTO 0);
206 crate_id : IN std_logic_vector (1 DOWNTO 0);
207 trigger_id : IN std_logic_vector (47 DOWNTO 0);
208 trigger : IN std_logic ;
209 s_trigger : IN std_logic ;
210 new_config : IN std_logic ;
211 config_started : OUT std_logic := '0';
212 adc_data_array : IN adc_data_array_type ;
213 adc_oeb : OUT std_logic := '1';
214 adc_otr : IN std_logic_vector (3 DOWNTO 0);
215 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
216 drs_dwrite : OUT std_logic := '1';
217 drs_clk_en : OUT std_logic := '0';
218 drs_read_s_cell : OUT std_logic := '0';
219 drs_read_s_cell_ready : IN std_logic ;
220 drs_s_cell_array : IN drs_s_cell_array_type
221 );
222 END COMPONENT;
223 COMPONENT drs_pulser_dummy
224 PORT (
225 CLK : IN std_logic;
226 SROUT_in_0 : IN std_logic;
227 SROUT_in_1 : IN std_logic;
228 SROUT_in_2 : IN std_logic;
229 SROUT_in_3 : IN std_logic;
230 start_endless_mode : IN std_logic;
231 start_read_stop_pos_mode : IN std_logic;
232 RSRLOAD : OUT std_logic := '0';
233 SRCLK : OUT std_logic := '0';
234 stop_pos : OUT drs_s_cell_array_type;
235 stop_pos_valid : OUT std_logic := '0'
236 );
237 END COMPONENT;
238 COMPONENT memory_manager
239 PORT (
240 clk : IN std_logic ;
241 config_start : IN std_logic ;
242 ram_write_ready : IN std_logic ;
243 roi_array : IN roi_array_type ;
244 ram_write_ea : OUT std_logic := '0';
245 config_ready : OUT std_logic := '0';
246 config_started : OUT std_logic := '0';
247 roi_max : OUT roi_max_type := (others => conv_std_logic_vector (0, 11));
248 package_length : OUT std_logic_vector (15 DOWNTO 0) := (others => '0');
249 wiz_ram_start_addr : OUT std_logic_vector (13 DOWNTO 0) := (others => '0');
250 wiz_write_length : OUT std_logic_vector (16 DOWNTO 0) := (others => '0');
251 wiz_number_of_channels : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
252 wiz_write_ea : OUT std_logic := '0';
253 wiz_write_header : OUT std_logic := '0';
254 wiz_write_end : OUT std_logic := '0';
255 wiz_busy : IN std_logic ;
256 ram_start_addr : OUT std_logic_vector (11 DOWNTO 0) := (others => '0')
257 );
258 END COMPONENT;
259 COMPONENT spi_interface
260 PORT (
261 clk_50MHz : IN std_logic ;
262 config_start : IN std_logic ;
263 dac_array : IN dac_array_type ;
264 config_ready : OUT std_logic ;
265 config_started : OUT std_logic := '0';
266 dac_cs : OUT std_logic ;
267 mosi : OUT std_logic := '0';
268 sclk : OUT std_logic ;
269 sensor_array : OUT sensor_array_type ;
270 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
271 sensor_ready : OUT std_logic ;
272 sio : INOUT std_logic
273 );
274 END COMPONENT;
275 COMPONENT w5300_modul
276 PORT (
277 clk : IN std_logic ;
278 wiz_reset : OUT std_logic := '1';
279 addr : OUT std_logic_vector (9 DOWNTO 0);
280 data : INOUT std_logic_vector (15 DOWNTO 0);
281 cs : OUT std_logic := '1';
282 wr : OUT std_logic := '1';
283 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
284 rd : OUT std_logic := '1';
285 int : IN std_logic ;
286 write_length : IN std_logic_vector (16 DOWNTO 0);
287 ram_start_addr : IN std_logic_vector (13 DOWNTO 0);
288 ram_data : IN std_logic_vector (15 DOWNTO 0);
289 ram_addr : OUT std_logic_vector (13 DOWNTO 0);
290 data_valid : IN std_logic ;
291 busy : OUT std_logic := '1';
292 write_header_flag : IN std_logic ;
293 write_end_flag : IN std_logic ;
294 fifo_channels : IN std_logic_vector (3 DOWNTO 0);
295 s_trigger : OUT std_logic := '0';
296 new_config : OUT std_logic := '0';
297 config_started : IN std_logic ;
298 config_addr : OUT std_logic_vector (7 DOWNTO 0);
299 config_data : INOUT std_logic_vector (15 DOWNTO 0) := (others => 'Z');
300 config_wr_en : OUT std_logic := '0';
301 config_rd_en : OUT std_logic := '0';
302 config_busy : IN std_logic
303 );
304 END COMPONENT;
305 COMPONENT trigger_counter
306 PORT (
307 trigger_id : OUT std_logic_vector (47 DOWNTO 0);
308 trigger : IN std_logic ;
309 clk : IN std_logic
310 );
311 END COMPONENT;
312
313 -- Optional embedded configurations
314 -- pragma synthesis_off
315 FOR ALL : adc_buffer USE ENTITY FACT_FAD_lib.adc_buffer;
316 FOR ALL : clock_generator USE ENTITY FACT_FAD_lib.clock_generator;
317 FOR ALL : control_unit USE ENTITY FACT_FAD_lib.control_unit;
318 FOR ALL : dataRAM_64bit_16bit USE ENTITY FACT_FAD_lib.dataRAM_64bit_16bit;
319 FOR ALL : data_generator USE ENTITY FACT_FAD_lib.data_generator;
320 FOR ALL : drs_pulser_dummy USE ENTITY FACT_FAD_lib.drs_pulser_dummy;
321 FOR ALL : memory_manager USE ENTITY FACT_FAD_lib.memory_manager;
322 FOR ALL : spi_interface USE ENTITY FACT_FAD_lib.spi_interface;
323 FOR ALL : trigger_counter USE ENTITY FACT_FAD_TB_lib.trigger_counter;
324 FOR ALL : w5300_modul USE ENTITY FACT_FAD_lib.w5300_modul;
325 -- pragma synthesis_on
326
327
328BEGIN
329
330 -- Instance port mappings.
331 U_3 : adc_buffer
332 PORT MAP (
333 clk_ps => CLK_25_PS_internal,
334 adc_data_array => adc_data_array,
335 adc_otr_array => adc_otr_array,
336 adc_data_array_int => adc_data_array_int,
337 adc_otr => adc_otr
338 );
339 U_0 : clock_generator
340 PORT MAP (
341 CLK => CLK,
342 CLK_25 => CLK_25,
343 CLK_25_PS => CLK_25_PS_internal,
344 CLK_50 => CLK_50_internal
345 );
346 U_2 : control_unit
347 PORT MAP (
348 clk => CLK_50_internal,
349 config_addr => config_addr,
350 config_rd_en => config_rd_en,
351 config_start => config_start_cm,
352 config_wr_en => config_wr_en,
353 config_busy => config_busy,
354 config_data_valid => config_data_valid,
355 config_ready => config_ready_cm,
356 config_started => config_started_cu,
357 dac_array => dac_array,
358 roi_array => roi_array,
359 config_data => config_data
360 );
361 I_main_dataRAM : dataRAM_64bit_16bit
362 PORT MAP (
363 clka => CLK_25,
364 dina => data_out,
365 addra => addr_out,
366 wea => write_ea,
367 clkb => CLK_50_internal,
368 addrb => ram_addr,
369 doutb => ram_data
370 );
371 I_main_data_generator : data_generator
372 PORT MAP (
373 clk => CLK_25,
374 data_out => data_out,
375 addr_out => addr_out,
376 write_ea => write_ea,
377 ram_start_addr => ram_start_addr,
378 ram_write_ea => ram_write_ea,
379 ram_write_ready => ram_write_ready,
380 config_start_mm => config_start,
381 config_start_cm => config_start_cm,
382 config_start_spi => config_start_spi,
383 config_ready_mm => config_ready,
384 config_ready_cm => config_ready_cm,
385 config_ready_spi => config_ready_spi,
386 config_started_mm => config_started_mm,
387 config_started_cm => config_started_cu,
388 config_started_spi => config_started_spi,
389 roi_array => roi_array,
390 roi_max => roi_max,
391 sensor_array => sensor_array,
392 sensor_ready => sensor_ready,
393 dac_array => dac_array,
394 package_length => package_length,
395 board_id => board_id,
396 crate_id => crate_id,
397 trigger_id => trigger_id,
398 trigger => trigger,
399 s_trigger => s_trigger,
400 new_config => new_config,
401 config_started => config_started,
402 adc_data_array => adc_data_array_int,
403 adc_oeb => adc_oeb,
404 adc_otr => adc_otr,
405 drs_channel_id => drs_channel_id,
406 drs_dwrite => drs_dwrite,
407 drs_clk_en => drs_clk_en,
408 drs_read_s_cell => drs_read_s_cell,
409 drs_read_s_cell_ready => drs_read_s_cell_ready,
410 drs_s_cell_array => drs_s_cell_array
411 );
412 U_1 : drs_pulser_dummy
413 PORT MAP (
414 CLK => CLK_25,
415 start_endless_mode => drs_clk_en,
416 start_read_stop_pos_mode => drs_read_s_cell,
417 SROUT_in_0 => SROUT_in_0,
418 SROUT_in_1 => SROUT_in_1,
419 SROUT_in_2 => SROUT_in_2,
420 SROUT_in_3 => SROUT_in_3,
421 stop_pos => drs_s_cell_array,
422 stop_pos_valid => drs_read_s_cell_ready,
423 RSRLOAD => RSRLOAD,
424 SRCLK => SRCLK
425 );
426 I_main_memory_manager : memory_manager
427 PORT MAP (
428 clk => CLK_25,
429 config_start => config_start,
430 ram_write_ready => ram_write_ready,
431 roi_array => roi_array,
432 ram_write_ea => ram_write_ea,
433 config_ready => config_ready,
434 config_started => config_started_mm,
435 roi_max => roi_max,
436 package_length => package_length,
437 wiz_ram_start_addr => wiz_ram_start_addr,
438 wiz_write_length => wiz_write_length,
439 wiz_number_of_channels => wiz_number_of_channels,
440 wiz_write_ea => wiz_write_ea,
441 wiz_write_header => wiz_write_header,
442 wiz_write_end => wiz_write_end,
443 wiz_busy => wiz_busy,
444 ram_start_addr => ram_start_addr
445 );
446 U_4 : spi_interface
447 PORT MAP (
448 clk_50MHz => CLK_50_internal,
449 config_start => config_start_spi,
450 dac_array => dac_array,
451 config_ready => config_ready_spi,
452 config_started => config_started_spi,
453 dac_cs => dac_cs,
454 mosi => mosi,
455 sclk => sclk,
456 sensor_array => sensor_array,
457 sensor_cs => sensor_cs,
458 sensor_ready => sensor_ready,
459 sio => sio
460 );
461 I_main_ethernet : w5300_modul
462 PORT MAP (
463 clk => CLK_50_internal,
464 wiz_reset => wiz_reset,
465 addr => wiz_addr,
466 data => wiz_data,
467 cs => wiz_cs,
468 wr => wiz_wr,
469 led => led,
470 rd => wiz_rd,
471 int => wiz_int,
472 write_length => wiz_write_length,
473 ram_start_addr => wiz_ram_start_addr,
474 ram_data => ram_data,
475 ram_addr => ram_addr,
476 data_valid => wiz_write_ea,
477 busy => wiz_busy,
478 write_header_flag => wiz_write_header,
479 write_end_flag => wiz_write_end,
480 fifo_channels => wiz_number_of_channels,
481 s_trigger => s_trigger,
482 new_config => new_config,
483 config_started => config_started,
484 config_addr => config_addr,
485 config_data => config_data,
486 config_wr_en => config_wr_en,
487 config_rd_en => config_rd_en,
488 config_busy => config_busy
489 );
490 I_main_ext_trigger : trigger_counter
491 PORT MAP (
492 trigger_id => trigger_id,
493 trigger => trigger,
494 clk => CLK_50_internal
495 );
496
497 -- Implicit buffered output assignments
498 CLK_25_PS <= CLK_25_PS_internal;
499 CLK_50 <= CLK_50_internal;
500
501END struct;
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