source: FPGA/FAD/FACT_FAD_lib/hdl/fad_testboard_struct.vhd@ 236

Last change on this file since 236 was 215, checked in by dneise, 16 years ago
initial commit (2nd part): only VHDL and UCF files were commited.
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1-- VHDL Entity FACT_FAD_lib.FAD_Testboard.symbol
2--
3-- Created:
4-- by - kai.UNKNOWN (E5PCXX)
5-- at - 11:34:39 18.05.2010
6--
7-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8--
9LIBRARY ieee;
10USE ieee.std_logic_1164.all;
11USE ieee.std_logic_arith.all;
12
13ENTITY FAD_Testboard IS
14 PORT(
15 clk : IN STD_LOGIC;
16 trigger : IN STD_LOGIC;
17 wiz_int : IN std_logic;
18 CLK_25_PS : OUT std_logic;
19 CLK_50 : OUT std_logic;
20 RSRLOAD : OUT std_logic := '0';
21 SRCLK : OUT std_logic := '0';
22 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
23 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
24 wiz_cs : OUT std_logic := '1';
25 wiz_rd : OUT std_logic := '1';
26 wiz_reset : OUT std_logic := '1';
27 wiz_wr : OUT std_logic := '1';
28 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
29 );
30
31-- Declarations
32
33END FAD_Testboard ;
34
35--
36-- VHDL Architecture FACT_FAD_lib.FAD_Testboard.struct
37--
38-- Created:
39-- by - kai.UNKNOWN (E5PCXX)
40-- at - 11:34:39 18.05.2010
41--
42-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
43--
44LIBRARY ieee;
45USE ieee.std_logic_1164.all;
46USE ieee.std_logic_arith.all;
47USE IEEE.NUMERIC_STD.all;
48
49LIBRARY FACT_FAD_lib;
50USE FACT_FAD_lib.fad_definitions.all;
51LIBRARY FACT_FAD_test_devices_lib;
52USE FACT_FAD_test_devices_lib.drs4_pack.all;
53USE ieee.std_logic_unsigned.all;
54
55LIBRARY FACT_FAD_lib;
56LIBRARY FACT_FAD_test_devices_lib;
57
58ARCHITECTURE struct OF FAD_Testboard IS
59
60 -- Architecture declarations
61
62 -- Internal signal declarations
63 SIGNAL SROUT_in_0 : std_logic;
64 SIGNAL SROUT_in_1 : std_logic;
65 SIGNAL SROUT_in_2 : std_logic;
66 SIGNAL SROUT_in_3 : std_logic;
67 SIGNAL adc_data : STD_LOGIC_VECTOR(11 DOWNTO 0);
68 SIGNAL adc_data_array : adc_data_array_type;
69 SIGNAL adc_oeb : STD_LOGIC;
70 SIGNAL adc_otr : STD_LOGIC;
71 SIGNAL adc_otr_array : std_logic_vector(3 DOWNTO 0);
72 SIGNAL board_id : std_logic_vector(3 DOWNTO 0);
73 SIGNAL crate_id : std_logic_vector(1 DOWNTO 0);
74 SIGNAL dac_cs : std_logic;
75 SIGNAL drs_channel_id : std_logic_vector(3 DOWNTO 0) := (others => '0');
76 SIGNAL drs_dwrite : std_logic := '1';
77 SIGNAL rst : STD_LOGIC;
78 SIGNAL sclk : std_logic;
79 SIGNAL sensor_cs : std_logic_vector(3 DOWNTO 0);
80 SIGNAL sio : std_logic;
81 SIGNAL trigger_int : STD_LOGIC := '0';
82
83 -- Implicit buffer signal declarations
84 SIGNAL CLK_25_PS_internal : std_logic;
85
86
87 -- Component Declarations
88 COMPONENT FAD_main
89 PORT (
90 CLK : IN std_logic ;
91 SROUT_in_0 : IN std_logic ;
92 SROUT_in_1 : IN std_logic ;
93 SROUT_in_2 : IN std_logic ;
94 SROUT_in_3 : IN std_logic ;
95 adc_data_array : IN adc_data_array_type ;
96 adc_otr_array : IN std_logic_vector (3 DOWNTO 0);
97 board_id : IN std_logic_vector (3 DOWNTO 0);
98 crate_id : IN std_logic_vector (1 DOWNTO 0);
99 trigger : IN std_logic ;
100 wiz_int : IN std_logic ;
101 CLK_25_PS : OUT std_logic ;
102 CLK_50 : OUT std_logic ;
103 RSRLOAD : OUT std_logic := '0';
104 SRCLK : OUT std_logic := '0';
105 adc_oeb : OUT std_logic := '1';
106 dac_cs : OUT std_logic ;
107 drs_channel_id : OUT std_logic_vector (3 DOWNTO 0) := (others => '0');
108 drs_dwrite : OUT std_logic := '1';
109 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
110 sclk : OUT std_logic ;
111 sensor_cs : OUT std_logic_vector (3 DOWNTO 0);
112 wiz_addr : OUT std_logic_vector (9 DOWNTO 0);
113 wiz_cs : OUT std_logic := '1';
114 wiz_rd : OUT std_logic := '1';
115 wiz_reset : OUT std_logic := '1';
116 wiz_wr : OUT std_logic := '1';
117 sio : INOUT std_logic ;
118 wiz_data : INOUT std_logic_vector (15 DOWNTO 0)
119 );
120 END COMPONENT;
121 COMPONENT FAD_adc_emulator
122 PORT (
123 adc_oeb : IN STD_LOGIC ;
124 clk : IN STD_LOGIC ;
125 rst : IN STD_LOGIC ;
126 adc_data : OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
127 adc_otr : OUT STD_LOGIC
128 );
129 END COMPONENT;
130 COMPONENT debouncer
131 GENERIC (
132 WIDTH : INTEGER := 17
133 );
134 PORT (
135 clk : IN STD_LOGIC ;
136 -- rst : in STD_LOGIC;
137 trigger_in : IN STD_LOGIC ;
138 trigger_out : OUT STD_LOGIC := '0'
139 );
140 END COMPONENT;
141 COMPONENT max6662_emulator
142 GENERIC (
143 DRS_TEMPERATURE : integer := 51
144 );
145 PORT (
146 sclk : IN std_logic;
147 sensor_cs : IN std_logic_vector (3 DOWNTO 0);
148 sio : INOUT std_logic
149 );
150 END COMPONENT;
151
152 -- Optional embedded configurations
153 -- pragma synthesis_off
154 FOR ALL : FAD_adc_emulator USE ENTITY FACT_FAD_test_devices_lib.FAD_adc_emulator;
155 FOR ALL : FAD_main USE ENTITY FACT_FAD_lib.FAD_main;
156 FOR ALL : debouncer USE ENTITY FACT_FAD_test_devices_lib.debouncer;
157 FOR ALL : max6662_emulator USE ENTITY FACT_FAD_test_devices_lib.max6662_emulator;
158 -- pragma synthesis_on
159
160
161BEGIN
162 -- Architecture concurrent statements
163 -- HDL Embedded Text Block 1 eb_ID
164 -- hard-wired IDs
165 board_id <= "0101";
166 crate_id <= "01";
167
168 -- HDL Embedded Text Block 2 eb1
169 -- eb1 2
170 adc_data_array (0) <= adc_data;
171 adc_data_array (1) <= adc_data;
172 adc_data_array (2) <= adc_data;
173 adc_data_array (3) <= adc_data;
174 adc_otr_array(0) <= adc_otr;
175 adc_otr_array(1) <= adc_otr;
176 adc_otr_array(2) <= adc_otr;
177 adc_otr_array(3) <= adc_otr;
178
179 -- HDL Embedded Text Block 3 eb2
180 -- eb2 3
181 SROUT_in_0 <= '1';
182 SROUT_in_1 <= '0';
183 SROUT_in_2 <= '1';
184 SROUT_in_3 <= '0';
185
186
187
188 -- Instance port mappings.
189 I_testboard_main : FAD_main
190 PORT MAP (
191 CLK => clk,
192 SROUT_in_0 => SROUT_in_0,
193 SROUT_in_1 => SROUT_in_1,
194 SROUT_in_2 => SROUT_in_2,
195 SROUT_in_3 => SROUT_in_3,
196 adc_data_array => adc_data_array,
197 adc_otr_array => adc_otr_array,
198 board_id => board_id,
199 crate_id => crate_id,
200 trigger => trigger_int,
201 wiz_int => wiz_int,
202 CLK_25_PS => CLK_25_PS_internal,
203 CLK_50 => CLK_50,
204 RSRLOAD => RSRLOAD,
205 SRCLK => SRCLK,
206 adc_oeb => adc_oeb,
207 dac_cs => dac_cs,
208 drs_channel_id => drs_channel_id,
209 drs_dwrite => drs_dwrite,
210 led => led,
211 sclk => sclk,
212 sensor_cs => sensor_cs,
213 wiz_addr => wiz_addr,
214 wiz_cs => wiz_cs,
215 wiz_rd => wiz_rd,
216 wiz_reset => wiz_reset,
217 wiz_wr => wiz_wr,
218 sio => sio,
219 wiz_data => wiz_data
220 );
221 I_testboard_adc : FAD_adc_emulator
222 PORT MAP (
223 adc_oeb => adc_oeb,
224 clk => CLK_25_PS_internal,
225 rst => rst,
226 adc_data => adc_data,
227 adc_otr => adc_otr
228 );
229 I_testboard_debouncer : debouncer
230 GENERIC MAP (
231 WIDTH => 12
232 )
233 PORT MAP (
234 clk => CLK_25_PS_internal,
235 trigger_in => trigger,
236 trigger_out => trigger_int
237 );
238 I0 : max6662_emulator
239 GENERIC MAP (
240 DRS_TEMPERATURE => 51
241 )
242 PORT MAP (
243 sclk => sclk,
244 sio => sio,
245 sensor_cs => sensor_cs
246 );
247
248 -- Implicit buffered output assignments
249 CLK_25_PS <= CLK_25_PS_internal;
250
251END struct;
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