source: FPGA/FAD/FACT_FAD_lib/hdl/w5300_modul.vhd@ 228

Last change on this file since 228 was 215, checked in by dneise, 14 years ago
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1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 PORT(
34 clk : IN std_logic;
35 wiz_reset : OUT std_logic := '1';
36 addr : OUT std_logic_vector (9 DOWNTO 0);
37 data : INOUT std_logic_vector (15 DOWNTO 0);
38 cs : OUT std_logic := '1';
39 wr : OUT std_logic := '1';
40 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
41 rd : OUT std_logic := '1';
42 int : IN std_logic;
43 write_length : IN std_logic_vector (16 DOWNTO 0);
44 ram_start_addr : IN std_logic_vector (13 DOWNTO 0);
45 ram_data : IN std_logic_vector (15 DOWNTO 0);
46 ram_addr : OUT std_logic_vector (13 DOWNTO 0);
47 data_valid : IN std_logic;
48 busy : OUT std_logic := '1';
49 write_header_flag, write_end_flag : IN std_logic;
50 fifo_channels : IN std_logic_vector (3 downto 0);
51 s_trigger : OUT std_logic := '0';
52 new_config : OUT std_logic := '0';
53 config_started : in std_logic;
54 config_addr : out std_logic_vector (7 downto 0);
55 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
56 config_wr_en : out std_logic := '0';
57 config_rd_en : out std_logic := '0';
58 config_busy : in std_logic
59 );
60
61-- Declarations
62
63END w5300_modul ;
64
65architecture Behavioral of w5300_modul is
66
67type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
68 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1,
69 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);
70type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
71 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
72type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
73type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
74type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
75
76signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
77
78signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
79signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
80signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
81signal adc_data_addr : std_logic_vector (13 DOWNTO 0);
82
83signal state_init, next_state , next_state_tmp : state_init_type := RESET;
84signal count : std_logic_vector (2 downto 0) := "000";
85signal state_write : state_write_type := WR_START;
86signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
87signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
88signal state_read_data : state_read_data_type := RD_1;
89
90signal interrupt_ignore : std_logic := '1';
91signal int_flag : std_logic := '0';
92signal ram_access : std_logic := '0';
93
94signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
95signal data_cnt : integer := 0;
96signal drs_cnt : integer :=0;
97signal channel_cnt : integer range 0 to 9 :=0;
98signal socket_cnt : std_logic_vector (2 downto 0) := "000";
99signal roi_max : std_logic_vector (10 downto 0);
100signal data_end : integer := 0;
101
102signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
103signal write_length_bytes : std_logic_vector (16 downto 0);
104
105signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
106signal chk_recv_cntr : integer range 0 to 10000 := 0;
107signal rx_packets_cnt : std_logic_vector (15 downto 0);
108signal next_packet_data : std_logic := '0';
109signal new_config_flag : std_logic := '0';
110
111signal trigger_stop : std_logic := '1';
112
113signal local_write_length : std_logic_vector (16 DOWNTO 0);
114signal local_ram_start_addr : std_logic_vector (13 DOWNTO 0);
115signal local_ram_addr : std_logic_vector (13 downto 0);
116signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
117signal local_write_header_flag, local_write_end_flag : std_logic;
118signal local_fifo_channels : std_logic_vector (3 downto 0);
119
120begin
121
122 --synthesis translate_off
123 RST_TIME <= X"00120";
124 --synthesis translate_on
125
126 w5300_init_proc : process (clk, int)
127 begin
128
129 if rising_edge (clk) then
130
131 -- Interrupt low
132 if (int = '0') and (interrupt_ignore = '0') then
133 case state_interrupt_1 is
134 when IR1_01 =>
135 int_flag <= '1';
136 busy <= '1';
137 state_interrupt_1 <= IR1_02;
138 when IR1_02 =>
139 state_interrupt_1 <= IR1_03;
140 when IR1_03 =>
141 state_init <= INTERRUPT;
142 socket_cnt <= "000";
143 ram_access <= '0';
144 zaehler <= X"00000";
145 count <= "000";
146 int_flag <= '0';
147 interrupt_ignore <= '1';
148 state_interrupt_1 <= IR1_04;
149 when others =>
150 null;
151 end case;
152 end if; -- int = '0'
153
154 if int_flag = '0' then
155 case state_init is
156 -- Interrupt
157 when INTERRUPT =>
158 case state_interrupt_2 is
159 when IR2_01 =>
160 par_addr <= W5300_IR;
161 state_init <= READ_REG;
162 next_state <= INTERRUPT;
163 state_interrupt_2 <= IR2_02;
164 when IR2_02 =>
165 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
166 state_interrupt_2 <= IR2_03;
167 else
168 socket_cnt <= socket_cnt + 1;
169 if (socket_cnt = 7) then
170 state_interrupt_2 <= IR2_06;
171 else
172 state_interrupt_2 <= IR2_02;
173 end if;
174 end if;
175 when IR2_03 =>
176 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
177 state_init <= READ_REG;
178 next_state <= INTERRUPT;
179 state_interrupt_2 <= IR2_04;
180 when IR2_04 =>
181 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
182 par_data <= data_read; -- clear Interrupts
183 state_init <= WRITE_REG;
184 next_state <= INTERRUPT;
185 state_interrupt_2 <= IR2_05;
186 when IR2_05 =>
187 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
188 par_data <= X"0010"; -- CLOSE
189 state_init <= WRITE_REG;
190 next_state <= INTERRUPT;
191 socket_cnt <= socket_cnt + 1;
192 if (socket_cnt = 7) then
193 state_interrupt_2 <= IR2_06;
194 else
195 state_interrupt_2 <= IR2_01;
196 end if;
197
198 when IR2_06 =>
199 state_interrupt_1 <= IR1_01;
200 state_interrupt_2 <= IR2_01;
201 socket_cnt <= "000";
202 state_init <= RESET;
203 end case;
204
205 -- reset W5300
206 when RESET =>
207 zaehler <= zaehler + 1;
208 wiz_reset <= '0';
209 led <= X"FF";
210 if (zaehler >= X"00064") then -- wait 2µs
211 wiz_reset <= '1';
212 end if;
213 if (zaehler = RST_TIME) then -- wait 10ms
214 zaehler <= X"00000";
215 socket_cnt <= "000";
216 count <= "000";
217 ram_access <= '0';
218 interrupt_ignore <= '0';
219 rd <= '1';
220 wr <= '1';
221 cs <= '1';
222 state_write <= WR_START;
223 state_init <= INIT;
224 end if;
225
226 -- Init
227 when INIT =>
228 par_addr <= W5300_MR;
229 par_data <= X"0000";
230 state_init <= WRITE_REG;
231 next_state <= IM;
232
233 -- Interrupt Mask
234 when IM =>
235 par_addr <= W5300_IMR;
236 par_data <= X"00FF"; -- S0-S7 Interrupts
237 state_init <= WRITE_REG;
238 next_state <= MT;
239
240 -- Memory Type
241 when MT =>
242 par_addr <= W5300_MTYPER;
243 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
244 state_init <= WRITE_REG;
245 next_state <= STX;
246
247 -- Socket TX Memory Size
248 when STX =>
249 par_data <= X"0F0F"; -- 15K TX
250
251 par_addr <= W5300_TMS01R;
252 state_init <=WRITE_REG;
253 next_state <= STX1;
254 when STX1 =>
255 par_addr <= W5300_TMS23R;
256 state_init <=WRITE_REG;
257 next_state <= STX2;
258 when STX2 =>
259 par_addr <= W5300_TMS45R;
260 state_init <=WRITE_REG;
261 next_state <= STX3;
262 when STX3 =>
263 par_addr <= W5300_TMS67R;
264 state_init <=WRITE_REG;
265 next_state <= SRX;
266
267 -- Socket RX Memory Size
268 when SRX =>
269 par_data <= X"0101"; -- 1K RX
270
271 par_addr <= W5300_RMS01R;
272 state_init <=WRITE_REG;
273 next_state <= SRX1;
274 when SRX1 =>
275 par_addr <= W5300_RMS23R;
276 state_init <=WRITE_REG;
277 next_state <= SRX2;
278 when SRX2 =>
279 par_addr <= W5300_RMS45R;
280 state_init <=WRITE_REG;
281 next_state <= SRX3;
282 when SRX3 =>
283 par_addr <= W5300_RMS67R;
284 state_init <=WRITE_REG;
285 next_state <= MAC;
286
287 -- MAC
288 when MAC =>
289 par_addr <= W5300_SHAR;
290 par_data <= MAC_ADDRESS (0);
291 state_init <= WRITE_REG;
292 next_state <= MAC1;
293 when MAC1 =>
294 par_addr <= W5300_SHAR + 2;
295 par_data <= MAC_ADDRESS (1);
296 state_init <= WRITE_REG;
297 next_state <= MAC2;
298 when MAC2 =>
299 par_addr <= W5300_SHAR + 4;
300 par_data <= MAC_ADDRESS (2);
301 state_init <= WRITE_REG;
302 next_state <= GW;
303
304 -- Gateway
305 when GW =>
306 par_addr <= W5300_GAR;
307 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
308 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
309 state_init <= WRITE_REG;
310 next_state <= GW1;
311 when GW1 =>
312 par_addr <= W5300_GAR + 2;
313 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
314 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
315 state_init <= WRITE_REG;
316 next_state <= SNM;
317
318 -- Subnet Mask
319 when SNM =>
320 par_addr <= W5300_SUBR;
321 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
322 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
323 state_init <= WRITE_REG;
324 next_state <= SNM1;
325 when SNM1 =>
326 par_addr <= W5300_SUBR + 2;
327 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
328 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
329 state_init <= WRITE_REG;
330 next_state <= IP;
331 -- Own IP-Address
332 when IP =>
333 par_addr <= W5300_SIPR;
334 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
335 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
336 state_init <= WRITE_REG;
337 next_state <= IP1;
338 when IP1 =>
339 par_addr <= W5300_SIPR + 2;
340 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
341 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
342 state_init <= WRITE_REG;
343 next_state <= SI;
344
345 -- Socket Init
346 when SI =>
347 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
348 par_data <= X"0101"; -- ALIGN, TCP
349 state_init <= WRITE_REG;
350 next_state <= SI1;
351 -- Sx Interrupt Mask
352 when SI1 =>
353 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
354 par_data <= X"000A"; -- TIMEOUT, DISCON
355 state_init <= WRITE_REG;
356 next_state <= SI2;
357 when SI2 =>
358 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
359 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
360 state_init <= WRITE_REG;
361 next_state <= SI3;
362 when SI3 =>
363 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
364 par_data <= X"0001"; -- OPEN
365 state_init <= WRITE_REG;
366 next_state <= SI4;
367 when SI4 =>
368 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
369 state_init <= READ_REG;
370 next_state <= SI5;
371 when SI5 =>
372 if (data_read (7 downto 0) = X"13") then -- is open?
373 state_init <= SI6;
374 else
375 state_init <= SI4;
376 end if;
377 when SI6 =>
378 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
379 par_data <= X"0002"; -- LISTEN
380 state_init <= WRITE_REG;
381 socket_cnt <= socket_cnt + 1;
382 if (socket_cnt = 7) then
383 socket_cnt <= "000";
384 next_state <= ESTABLISH; -- All Sockets open
385 else
386 next_state <= SI; -- Next Socket
387 end if;
388 -- End Socket Init
389
390 when ESTABLISH =>
391 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
392 state_init <= READ_REG;
393 next_state <= EST1;
394 when EST1 =>
395 led <= data_read (7 downto 0);
396 case data_read (7 downto 0) is
397 when X"17" => -- established
398 if (socket_cnt = 7) then
399 socket_cnt <= "000";
400 busy <= '0';
401 state_init <= MAIN;
402 else
403 socket_cnt <= socket_cnt + 1;
404 state_init <= ESTABLISH;
405 end if;
406 when others =>
407 state_init <= ESTABLISH;
408 end case;
409
410 when CONFIG =>
411 led <= X"F0";
412 new_config <= '1';
413 if (config_started = '1') then
414 led <= X"0F";
415 new_config <= '0';
416 busy <= '0';
417 state_init <= MAIN;
418 end if;
419
420 -- main "loop"
421 when MAIN =>
422 if (trigger_stop = '1') then
423 s_trigger <= '0';
424 end if;
425 if (chk_recv_cntr = 1000) then
426 chk_recv_cntr <= 0;
427 state_read_data <= RD_1;
428 state_init <= READ_DATA;
429 busy <= '1';
430 else
431 chk_recv_cntr <= chk_recv_cntr + 1;
432 if (data_valid = '1') then
433 local_write_length <= write_length;
434 local_ram_start_addr <= ram_start_addr;
435 local_ram_addr <= (others => '0');
436 local_write_header_flag <= write_header_flag;
437 local_write_end_flag <= write_end_flag;
438 local_fifo_channels <= fifo_channels;
439 next_state <= MAIN;
440 state_init <= WRITE_DATA;
441 busy <= '1';
442 end if;
443 end if;
444
445 -- read data from socket 0
446 when READ_DATA =>
447 case state_read_data is
448 when RD_1 =>
449 par_addr <= W5300_S0_RX_RSR;
450 state_init <= READ_REG;
451 next_state <= READ_DATA;
452 state_read_data <= RD_2;
453 when RD_2 =>
454 socket_rx_received (31 downto 16) <= data_read;
455 par_addr <= W5300_S0_RX_RSR + X"2";
456 state_init <= READ_REG;
457 next_state <= READ_DATA;
458 state_read_data <= RD_3;
459 when RD_3 =>
460 socket_rx_received (15 downto 0) <= data_read;
461 state_read_data <= RD_4;
462 when RD_4 =>
463 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
464 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
465 state_read_data <= RD_5;
466 else
467 busy <= '0';
468 state_init <= MAIN;
469 end if;
470 when RD_5 =>
471 if (rx_packets_cnt > 0) then
472 rx_packets_cnt <= rx_packets_cnt - '1';
473 par_addr <= W5300_S0_RX_FIFOR;
474 state_init <= READ_REG;
475 next_state <= READ_DATA;
476 state_read_data <= RD_6;
477 else
478 state_read_data <= RD_END;
479-- if (new_config_flag = '1') then
480-- new_config_flag <= '0';
481-- state_init <= CONFIG;
482-- else
483-- busy <= '0';
484-- state_init <= MAIN;
485-- end if;
486 end if;
487 when RD_6 =>
488 led <= data_read (15 downto 8);
489 -- read command
490 if (next_packet_data = '0') then
491 case data_read (15 downto 8) is
492 when CMD_TRIGGER =>
493 trigger_stop <= '1';
494 s_trigger <= '1';
495 state_read_data <= RD_WAIT;
496 when CMD_TRIGGER_C =>
497 trigger_stop <= '0';
498 s_trigger <= '1';
499 state_read_data <= RD_WAIT;
500 when CMD_TRIGGER_S =>
501 trigger_stop <= '1';
502 state_read_data <= RD_WAIT;
503 when CMD_WRITE =>
504 next_packet_data <= '1';
505 config_addr <= data_read (7 downto 0);
506 state_read_data <= RD_5;
507 when others =>
508 state_read_data <= RD_5;
509 end case;
510 -- read data
511 else
512 if (config_busy = '0') then
513 config_data <= data_read;
514 config_wr_en <= '1';
515 new_config_flag <= '1';
516 next_packet_data <= '0';
517 state_read_data <= RD_WAIT;
518 end if;
519 end if;
520 when RD_WAIT =>
521 state_read_data <= RD_WAIT1;
522 when RD_WAIT1 =>
523 config_data <= (others => 'Z');
524 config_wr_en <= '0';
525 state_read_data <= RD_5;
526 when RD_END =>
527 par_addr <= W5300_S0_CR;
528 par_data <= X"0040"; -- RECV
529 state_init <= WRITE_REG;
530 if (new_config_flag = '1') then
531 new_config_flag <= '0';
532 next_state <= CONFIG;
533 else
534 busy <= '0';
535 next_state <= MAIN;
536 end if;
537
538 end case; -- state_data_read
539
540
541
542 when WRITE_DATA =>
543 case state_write is
544 when WR_START =>
545 if (local_write_header_flag = '1') then
546 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
547 end if;
548 state_write <= WR_WAIT1;
549 when WR_WAIT1 =>
550 state_write <= WR_LENGTH;
551 when WR_LENGTH =>
552 if (local_write_header_flag = '1') then
553 local_socket_nr <= ram_data (2 downto 0);
554 end if;
555 next_state_tmp <= next_state;
556 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
557 data_cnt <= 0;
558 state_write <= WR_01;
559 -- Check FIFO Size
560 when WR_01 =>
561 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
562 state_init <= READ_REG;
563 next_state <= WRITE_DATA;
564 state_write <= WR_02;
565 when WR_02 =>
566 socket_tx_free (31 downto 16) <= data_read;
567 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
568 state_init <= READ_REG;
569 next_state <= WRITE_DATA;
570 state_write <= WR_03;
571 when WR_03 =>
572 socket_tx_free (15 downto 0) <= data_read;
573 state_write <= WR_04;
574 when WR_04 =>
575 if (socket_tx_free (16 downto 0) < write_length_bytes) then
576 state_write <= WR_01;
577 else
578 if (local_write_header_flag = '1') then
579 state_write <= WR_FIFO;
580 else
581 state_write <= WR_ADC;
582 end if;
583 end if;
584
585 -- Fill FIFO
586
587 -- Write Header
588 when WR_FIFO =>
589 ram_addr <= local_ram_start_addr + local_ram_addr;
590 state_write <= WR_FIFO1;
591 when WR_FIFO1 =>
592 data_cnt <= data_cnt + 1;
593 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
594 local_ram_addr <= local_ram_addr + 1;
595 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
596 local_ram_addr <= local_ram_addr + 2;
597 end if;
598 if (data_cnt = 9) then -- skip empty words
599 local_ram_addr <= local_ram_addr + 4;
600 end if;
601 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
602 ram_access <= '1';
603 state_init <= WRITE_REG;
604 next_state <= WRITE_DATA;
605 state_write <= WR_FIFO;
606 else
607 state_write <= WR_ADC;
608 end if;
609 -- End Write Header
610
611 -- Write ADC-Data
612 ---- Start...
613 when WR_ADC =>
614 adc_data_addr <= local_ram_start_addr + local_ram_addr;
615 drs_cnt <= 0;
616 channel_cnt <= 1;
617 data_cnt <= 0;
618 roi_max <= (others => '0');
619 data_end <= 3;
620 state_write <= WR_ADC1;
621
622 ---- Write Channel
623 when WR_ADC1 =>
624 -- read ROI and set end of Channel-Data
625 if (data_cnt = 3) then
626 data_end <= conv_integer (ram_data) + 3;
627 if (ram_data > roi_max) then
628 roi_max <= ram_data (10 downto 0);
629 end if;
630 end if;
631 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
632 state_write <= WR_ADC2;
633 when WR_ADC2 =>
634 if (data_cnt < data_end) then
635 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
636 ram_access <= '1';
637 state_init <= WRITE_REG;
638 next_state <= WRITE_DATA;
639 data_cnt <= data_cnt + 1;
640 state_write <= WR_ADC1;
641 else
642 -- Next DRS
643 if (drs_cnt < 3) then
644 drs_cnt <= drs_cnt + 1;
645 data_cnt <= 0;
646 data_end <= 3;
647 state_write <= WR_ADC1;
648 else
649 -- Next Channel
650 if (channel_cnt < local_fifo_channels) then
651 channel_cnt <= channel_cnt + 1;
652 roi_max <= (others => '0');
653 drs_cnt <= 0;
654 data_cnt <= 0;
655 data_end <= 3;
656 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
657 state_write <= WR_ADC1;
658 else
659 -- Ready
660 if (local_write_end_flag = '1') then
661 state_write <= WR_ENDFLAG;
662 else
663 state_write <= WR_05;
664 end if;
665 end if;
666 end if;
667 end if;
668 -- End Write ADC-Data
669
670 -- Write End Package Flag
671 when WR_ENDFLAG =>
672 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
673 state_write <= WR_ENDFLAG1;
674 when WR_ENDFLAG1 =>
675 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
676 ram_access <= '1';
677 state_init <= WRITE_REG;
678 next_state <= WRITE_DATA;
679 state_write <= WR_ENDFLAG2;
680 when WR_ENDFLAG2 =>
681 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
682 state_write <= WR_ENDFLAG3;
683 when WR_ENDFLAG3 =>
684 state_init <= WRITE_REG;
685 next_state <= WRITE_DATA;
686 state_write <= WR_05;
687
688 -- End Write End Package Flag
689
690 --Send FIFO
691 when WR_05 =>
692 ram_access <= '0';
693 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
694 par_data <= (0 => write_length_bytes (16), others => '0');
695 state_init <= WRITE_REG;
696 state_write <= WR_06;
697 when WR_06 =>
698 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
699 par_data <= write_length_bytes (15 downto 0);
700 state_init <= WRITE_REG;
701 state_write <= WR_07;
702 when WR_07 =>
703 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
704 par_data <= X"0020"; -- Send
705 state_init <= WRITE_REG;
706 state_write <= WR_08;
707 when others =>
708 busy <= '0';
709 state_init <= next_state_tmp;
710 state_write <= WR_START;
711 end case;
712 -- End WRITE_DATA
713
714 when READ_REG =>
715 case count is
716 when "000" =>
717 cs <= '0';
718 rd <= '0';
719 wr <= '1';
720 data <= (others => 'Z'); -- !!!!!!!!!!
721 count <= "001";
722 addr <= par_addr;
723 when "001" =>
724 count <= "010";
725 when "010" =>
726 count <= "100";
727 when "100" =>
728 data_read <= data;
729 count <= "110";
730 when "110" =>
731 count <= "111";
732 when "111" =>
733 cs <= '1';
734 rd <= '1';
735 count <= "000";
736 state_init <= next_state;
737 when others =>
738 null;
739 end case;
740
741 when WRITE_REG =>
742 case count is
743 when "000" =>
744 cs <= '0';
745 wr <= '0';
746 rd <= '1';
747 addr <= par_addr;
748 if (ram_access = '1') then
749 data <= ram_data;
750 else
751 data <= par_data;
752 end if;
753 count <= "100";
754 when "100" =>
755 count <= "101";
756 when "101" =>
757 count <= "110";
758 when "110" =>
759 cs <= '1';
760 wr <= '1';
761 state_init <= next_state;
762 count <= "000";
763 when others =>
764 null;
765 end case;
766
767 when others =>
768 null;
769 end case;
770 end if; -- int_flag = '0'
771
772 end if; -- rising_edge (clk)
773
774 end process w5300_init_proc;
775
776end Behavioral;
777
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