source: FPGA/FAD/FACT_FAD_test_devices_lib/clock_divider_beha.vhd@ 236

--
-- VHDL Architecture FACT_FAD_test_devices_lib.clock_divider.beha
--
-- Created:
--          by - Benjamin Krumm.UNKNOWN (EEPC8)
--          at - 14:13:37 25.03.2010
--
-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY clock_divider IS
  port (
    clk_in : in std_logic;
    clk_out : out std_logic
  );
END ENTITY clock_divider;

--
ARCHITECTURE beha OF clock_divider IS
  
  signal clk_intern : std_logic := '0';
  
BEGIN
  
  clk_out <= clk_intern;
  
  divide_clk_proc: process (clk_in)
  begin
    if rising_edge(clk_in) then
      clk_intern <= NOT clk_intern;
    end if;
  end process divide_clk_proc;
  
END ARCHITECTURE beha;