source: FPGA/FAD/FACT_FAD_test_devices_lib/drs4_emulator.vhd@ 236

Last change on this file since 236 was 215, checked in by dneise, 16 years ago
initial commit (2nd part): only VHDL and UCF files were commited.
  • Property svn:executable set to *
File size: 6.5 KB
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1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 10:38:03 01/11/2010
6-- Design Name:
7-- Module Name: drs4_emulator - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20-- hds interface_start
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.NUMERIC_STD.ALL;
24library FACT_FAD_test_devices_lib;
25use FACT_FAD_test_devices_lib.drs4_pack.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31ENTITY drs4_emulator IS
32 PORT(
33 analog_in : IN TYPE_analog_data;
34 wsrout : OUT STD_LOGIC;
35 srout : OUT STD_LOGIC;
36 srin : IN STD_LOGIC;
37 srclk : IN STD_LOGIC;
38 rsrload : IN STD_LOGIC;
39 a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
40 reset : IN STD_LOGIC;
41 analog_out : OUT TYPE_analog_data;
42 analog_addr : OUT TYPE_analog_addr;
43 dtap : OUT STD_LOGIC;
44 refclk : IN STD_LOGIC;
45 pllout : OUT STD_LOGIC;
46 dspeed : IN STD_LOGIC;
47 dwrite : IN STD_LOGIC;
48 denable : IN STD_LOGIC;
49 wsrin : IN STD_LOGIC;
50 stop_cell_reg : IN std_logic_vector (9 DOWNTO 0);
51 stop_cell_addr : OUT std_logic_vector (9 DOWNTO 0);
52 clk_50MHz : IN std_logic
53 );
54
55-- Declarations
56
57END drs4_emulator ;
58-- hds interface_end
59
60architecture Behavioral of drs4_emulator is
61
62 signal temp_addr : TYPE_analog_addr;
63 signal temp_dtap : std_logic := '1';
64 signal temp_stop_addr : std_logic_vector(9 downto 0);
65 signal stop_state : srout_state := SROUT_IDLE;
66 signal dtap_cnt : std_logic_vector(5 downto 0);
67
68begin
69
70 analog_addr(0) <= temp_addr(0);
71 analog_addr(1) <= temp_addr(1);
72 analog_addr(2) <= temp_addr(2);
73 analog_addr(3) <= temp_addr(3);
74 analog_addr(4) <= temp_addr(4);
75 analog_addr(5) <= temp_addr(5);
76 analog_addr(6) <= temp_addr(6);
77 analog_addr(7) <= temp_addr(7);
78 analog_addr(8) <= temp_addr(8);
79
80 stop_cell_addr <= temp_stop_addr;
81 dtap <= temp_dtap;
82
83 dtap_out_proc: process(clk_50MHz, reset, denable)
84 begin
85 if (reset = '0') then
86 temp_dtap <= '0';
87 dtap_cnt <= (others => '0');
88 elsif rising_edge(clk_50MHz) then
89 if (denable = '1') then
90 dtap_cnt <= std_logic_vector(unsigned(dtap_cnt) + to_unsigned(1,6));
91 if (unsigned(dtap_cnt) = 24) then
92 temp_dtap <= not temp_dtap;
93 dtap_cnt <= (others => '0');
94 end if;
95 end if;
96 end if;
97 end process dtap_out_proc;
98
99 write_stop_cell_proc: process(reset, rsrload, srclk, stop_cell_reg)
100 begin
101 if (reset = '0') then
102 temp_stop_addr <= (others => '0');
103 srout <= '0';
104 stop_state <= SROUT_IDLE;
105 elsif (rsrload = '1') then
106 stop_state <= SROUT_BIT9;
107 srout <= stop_cell_reg(9);
108 elsif falling_edge(srclk) then
109 case stop_state is
110 when SROUT_BIT9 =>
111 stop_state <= SROUT_BIT8;
112 srout <= stop_cell_reg(8);
113 when SROUT_BIT8 =>
114 stop_state <= SROUT_BIT7;
115 srout <= stop_cell_reg(7);
116 when SROUT_BIT7 =>
117 stop_state <= SROUT_BIT6;
118 srout <= stop_cell_reg(6);
119 when SROUT_BIT6 =>
120 stop_state <= SROUT_BIT5;
121 srout <= stop_cell_reg(5);
122 when SROUT_BIT5 =>
123 stop_state <= SROUT_BIT4;
124 srout <= stop_cell_reg(4);
125 when SROUT_BIT4 =>
126 stop_state <= SROUT_BIT3;
127 srout <= stop_cell_reg(3);
128 when SROUT_BIT3 =>
129 stop_state <= SROUT_BIT2;
130 srout <= stop_cell_reg(2);
131 when SROUT_BIT2 =>
132 stop_state <= SROUT_BIT1;
133 srout <= stop_cell_reg(1);
134 when SROUT_BIT1 =>
135 stop_state <= SROUT_BIT0;
136 srout <= stop_cell_reg(0);
137 when SROUT_BIT0 =>
138 srout <= '0';
139 temp_stop_addr <= std_logic_vector(unsigned(temp_stop_addr) + to_unsigned(1,10));
140 stop_state <= SROUT_IDLE;
141 when others =>
142 end case;
143 end if;
144 end process write_stop_cell_proc;
145
146
147 analog_out_proc: process (srclk, reset, rsrload)
148 begin
149 if (reset = '0') then
150 for i in 0 to 8 loop
151 temp_addr(i) <= (others => '0');
152-- temp_addr(i) <= stop_cell_reg;
153 analog_out(i) <= (others => 'Z');
154 end loop;
155 elsif rising_edge(srclk) then
156 if (dwrite = '0') then
157 case a is
158 when "0000" =>
159 analog_out(8) <= analog_in(0);
160 temp_addr(0) <= std_logic_vector(unsigned(temp_addr(0)) + to_unsigned(1,10));
161 when "0001" =>
162 analog_out(8) <= analog_in(1);
163 temp_addr(1) <= std_logic_vector(unsigned(temp_addr(1)) + to_unsigned(1,10));
164 when "0010" =>
165 analog_out(8) <= analog_in(2);
166 temp_addr(2) <= std_logic_vector(unsigned(temp_addr(2)) + to_unsigned(1,10));
167 when "0011" =>
168 analog_out(8) <= analog_in(3);
169 temp_addr(3) <= std_logic_vector(unsigned(temp_addr(3)) + to_unsigned(1,10));
170 when "0100" =>
171 analog_out(8) <= analog_in(4);
172 temp_addr(4) <= std_logic_vector(unsigned(temp_addr(4)) + to_unsigned(1,10));
173 when "0101" =>
174 analog_out(8) <= analog_in(5);
175 temp_addr(5) <= std_logic_vector(unsigned(temp_addr(5)) + to_unsigned(1,10));
176 when "0110" =>
177 analog_out(8) <= analog_in(6);
178 temp_addr(6) <= std_logic_vector(unsigned(temp_addr(6)) + to_unsigned(1,10));
179 when "0111" =>
180 analog_out(8) <= analog_in(7);
181 temp_addr(7) <= std_logic_vector(unsigned(temp_addr(7)) + to_unsigned(1,10));
182 when "1000" =>
183 analog_out(8) <= analog_in(8);
184 temp_addr(8) <= std_logic_vector(unsigned(temp_addr(8)) + to_unsigned(1,10));
185 when "1001" =>
186 for i in 0 to 8 loop
187 analog_out(i) <= analog_in(i);
188 temp_addr(i) <= std_logic_vector(unsigned(temp_addr(i)) + to_unsigned(1,10));
189 end loop;
190 when "1111" =>
191 for i in 0 to 8 loop
192 analog_out(i) <= (others => 'Z');
193 end loop;
194 when others =>
195 end case;
196 end if;
197 end if;
198 end process analog_out_proc;
199
200end Behavioral;
201
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