1 | ----------------------------------------------------------------------------------
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2 | -- Company:
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3 | -- Engineer:
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4 | --
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5 | -- Create Date: 10:38:03 01/11/2010
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6 | -- Design Name:
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7 | -- Module Name: drs4_emulator - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description:
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | -- hds interface_start
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21 | library IEEE;
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22 | use IEEE.STD_LOGIC_1164.ALL;
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23 | use IEEE.NUMERIC_STD.ALL;
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24 | library FACT_FAD_test_devices_lib;
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25 | use FACT_FAD_test_devices_lib.drs4_pack.all;
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26 |
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27 | ---- Uncomment the following library declaration if instantiating
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28 | ---- any Xilinx primitives in this code.
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29 | --library UNISIM;
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30 | --use UNISIM.VComponents.all;
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31 | ENTITY drs4_emulator IS
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32 | PORT(
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33 | analog_in : IN TYPE_analog_data;
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34 | wsrout : OUT STD_LOGIC;
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35 | srout : OUT STD_LOGIC;
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36 | srin : IN STD_LOGIC;
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37 | srclk : IN STD_LOGIC;
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38 | rsrload : IN STD_LOGIC;
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39 | a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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40 | reset : IN STD_LOGIC;
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41 | analog_out : OUT TYPE_analog_data;
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42 | analog_addr : OUT TYPE_analog_addr;
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43 | dtap : OUT STD_LOGIC;
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44 | refclk : IN STD_LOGIC;
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45 | pllout : OUT STD_LOGIC;
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46 | dspeed : IN STD_LOGIC;
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47 | dwrite : IN STD_LOGIC;
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48 | denable : IN STD_LOGIC;
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49 | wsrin : IN STD_LOGIC;
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50 | stop_cell_reg : IN std_logic_vector (9 DOWNTO 0);
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51 | stop_cell_addr : OUT std_logic_vector (9 DOWNTO 0);
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52 | clk_50MHz : IN std_logic
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53 | );
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54 |
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55 | -- Declarations
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56 |
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57 | END drs4_emulator ;
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58 | -- hds interface_end
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59 |
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60 | architecture Behavioral of drs4_emulator is
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61 |
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62 | signal temp_addr : TYPE_analog_addr;
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63 | signal temp_dtap : std_logic := '1';
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64 | signal temp_stop_addr : std_logic_vector(9 downto 0);
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65 | signal stop_state : srout_state := SROUT_IDLE;
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66 | signal dtap_cnt : std_logic_vector(5 downto 0);
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67 |
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68 | begin
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69 |
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70 | analog_addr(0) <= temp_addr(0);
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71 | analog_addr(1) <= temp_addr(1);
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72 | analog_addr(2) <= temp_addr(2);
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73 | analog_addr(3) <= temp_addr(3);
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74 | analog_addr(4) <= temp_addr(4);
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75 | analog_addr(5) <= temp_addr(5);
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76 | analog_addr(6) <= temp_addr(6);
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77 | analog_addr(7) <= temp_addr(7);
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78 | analog_addr(8) <= temp_addr(8);
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79 |
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80 | stop_cell_addr <= temp_stop_addr;
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81 | dtap <= temp_dtap;
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82 |
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83 | dtap_out_proc: process(clk_50MHz, reset, denable)
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84 | begin
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85 | if (reset = '0') then
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86 | temp_dtap <= '0';
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87 | dtap_cnt <= (others => '0');
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88 | elsif rising_edge(clk_50MHz) then
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89 | if (denable = '1') then
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90 | dtap_cnt <= std_logic_vector(unsigned(dtap_cnt) + to_unsigned(1,6));
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91 | if (unsigned(dtap_cnt) = 24) then
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92 | temp_dtap <= not temp_dtap;
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93 | dtap_cnt <= (others => '0');
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94 | end if;
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95 | end if;
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96 | end if;
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97 | end process dtap_out_proc;
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98 |
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99 | write_stop_cell_proc: process(reset, rsrload, srclk, stop_cell_reg)
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100 | begin
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101 | if (reset = '0') then
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102 | temp_stop_addr <= (others => '0');
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103 | srout <= '0';
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104 | stop_state <= SROUT_IDLE;
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105 | elsif (rsrload = '1') then
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106 | stop_state <= SROUT_BIT9;
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107 | srout <= stop_cell_reg(9);
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108 | elsif falling_edge(srclk) then
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109 | case stop_state is
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110 | when SROUT_BIT9 =>
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111 | stop_state <= SROUT_BIT8;
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112 | srout <= stop_cell_reg(8);
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113 | when SROUT_BIT8 =>
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114 | stop_state <= SROUT_BIT7;
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115 | srout <= stop_cell_reg(7);
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116 | when SROUT_BIT7 =>
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117 | stop_state <= SROUT_BIT6;
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118 | srout <= stop_cell_reg(6);
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119 | when SROUT_BIT6 =>
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120 | stop_state <= SROUT_BIT5;
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121 | srout <= stop_cell_reg(5);
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122 | when SROUT_BIT5 =>
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123 | stop_state <= SROUT_BIT4;
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124 | srout <= stop_cell_reg(4);
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125 | when SROUT_BIT4 =>
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126 | stop_state <= SROUT_BIT3;
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127 | srout <= stop_cell_reg(3);
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128 | when SROUT_BIT3 =>
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129 | stop_state <= SROUT_BIT2;
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130 | srout <= stop_cell_reg(2);
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131 | when SROUT_BIT2 =>
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132 | stop_state <= SROUT_BIT1;
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133 | srout <= stop_cell_reg(1);
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134 | when SROUT_BIT1 =>
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135 | stop_state <= SROUT_BIT0;
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136 | srout <= stop_cell_reg(0);
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137 | when SROUT_BIT0 =>
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138 | srout <= '0';
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139 | temp_stop_addr <= std_logic_vector(unsigned(temp_stop_addr) + to_unsigned(1,10));
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140 | stop_state <= SROUT_IDLE;
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141 | when others =>
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142 | end case;
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143 | end if;
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144 | end process write_stop_cell_proc;
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145 |
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146 |
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147 | analog_out_proc: process (srclk, reset, rsrload)
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148 | begin
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149 | if (reset = '0') then
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150 | for i in 0 to 8 loop
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151 | temp_addr(i) <= (others => '0');
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152 | -- temp_addr(i) <= stop_cell_reg;
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153 | analog_out(i) <= (others => 'Z');
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154 | end loop;
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155 | elsif rising_edge(srclk) then
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156 | if (dwrite = '0') then
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157 | case a is
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158 | when "0000" =>
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159 | analog_out(8) <= analog_in(0);
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160 | temp_addr(0) <= std_logic_vector(unsigned(temp_addr(0)) + to_unsigned(1,10));
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161 | when "0001" =>
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162 | analog_out(8) <= analog_in(1);
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163 | temp_addr(1) <= std_logic_vector(unsigned(temp_addr(1)) + to_unsigned(1,10));
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164 | when "0010" =>
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165 | analog_out(8) <= analog_in(2);
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166 | temp_addr(2) <= std_logic_vector(unsigned(temp_addr(2)) + to_unsigned(1,10));
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167 | when "0011" =>
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168 | analog_out(8) <= analog_in(3);
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169 | temp_addr(3) <= std_logic_vector(unsigned(temp_addr(3)) + to_unsigned(1,10));
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170 | when "0100" =>
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171 | analog_out(8) <= analog_in(4);
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172 | temp_addr(4) <= std_logic_vector(unsigned(temp_addr(4)) + to_unsigned(1,10));
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173 | when "0101" =>
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174 | analog_out(8) <= analog_in(5);
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175 | temp_addr(5) <= std_logic_vector(unsigned(temp_addr(5)) + to_unsigned(1,10));
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176 | when "0110" =>
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177 | analog_out(8) <= analog_in(6);
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178 | temp_addr(6) <= std_logic_vector(unsigned(temp_addr(6)) + to_unsigned(1,10));
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179 | when "0111" =>
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180 | analog_out(8) <= analog_in(7);
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181 | temp_addr(7) <= std_logic_vector(unsigned(temp_addr(7)) + to_unsigned(1,10));
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182 | when "1000" =>
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183 | analog_out(8) <= analog_in(8);
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184 | temp_addr(8) <= std_logic_vector(unsigned(temp_addr(8)) + to_unsigned(1,10));
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185 | when "1001" =>
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186 | for i in 0 to 8 loop
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187 | analog_out(i) <= analog_in(i);
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188 | temp_addr(i) <= std_logic_vector(unsigned(temp_addr(i)) + to_unsigned(1,10));
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189 | end loop;
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190 | when "1111" =>
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191 | for i in 0 to 8 loop
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192 | analog_out(i) <= (others => 'Z');
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193 | end loop;
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194 | when others =>
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195 | end case;
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196 | end if;
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197 | end if;
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198 | end process analog_out_proc;
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199 |
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200 | end Behavioral;
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201 |
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