source: FPGA/FAD/FACT_FAD_test_devices_lib/fad_dcm1_BEHAVIORAL.vhd@ 236

Last change on this file since 236 was 215, checked in by dneise, 16 years ago
initial commit (2nd part): only VHDL and UCF files were commited.
  • Property svn:executable set to *
File size: 8.5 KB
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1-- Coregen VHDL wrapper file modified by HDL Designer
2
3--------------------------------------------------------------------------------
4-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
5--------------------------------------------------------------------------------
6-- ____ ____
7-- / /\/ /
8-- /___/ \ / Vendor: Xilinx
9-- \ \ \/ Version : 10.1.03
10-- \ \ Application : xaw2vhdl
11-- / / Filename : fad_dcm1.vhd
12-- /___/ /\ Timestamp : 02/01/2010 10:18:45
13-- \ \ / \
14-- \___\/\___\
15--
16--Command: xaw2vhdl-st C:/DOKUME~1/FPGA_D~1/LOKALE~1/Temp/coregen_hds_tmp_project_files/FPGA_Developer/coregen/project/fad_dcm1.xaw C:/DOKUME~1/FPGA_D~1/LOKALE~1/Temp/coregen_hds_tmp_project_files/FPGA_Developer/coregen/project/fad_dcm1
17--Design Name: fad_dcm1
18--Device: xc3s700a-4fg484
19--
20-- Module fad_dcm1
21-- Written for synthesis tool: Precision
22
23library ieee;
24use ieee.std_logic_1164.ALL;
25use ieee.numeric_std.ALL;
26library UNISIM;
27use UNISIM.Vcomponents.ALL;
28
29entity fad_dcm1 is
30 port ( CLKIN_IN : in std_logic;
31 USER_RST_IN : in std_logic;
32 CLKIN_IBUFG_OUT : out std_logic;
33 CLK0_OUT : out std_logic;
34 CLK0_OUT1 : out std_logic;
35 CLK180_OUT : out std_logic;
36 LOCKED_OUT : out std_logic);
37end fad_dcm1;
38
39architecture BEHAVIORAL of fad_dcm1 is
40
41-- hds translate_off
42
43 attribute CLK_FEEDBACK : string ;
44 attribute CLKDV_DIVIDE : string ;
45 attribute CLKFX_DIVIDE : string ;
46 attribute CLKFX_MULTIPLY : string ;
47 attribute CLKIN_DIVIDE_BY_2 : string ;
48 attribute CLKIN_PERIOD : string ;
49 attribute CLKOUT_PHASE_SHIFT : string ;
50 attribute DESKEW_ADJUST : string ;
51 attribute DFS_FREQUENCY_MODE : string ;
52 attribute DLL_FREQUENCY_MODE : string ;
53 attribute DUTY_CYCLE_CORRECTION : string ;
54 attribute FACTORY_JF : string ;
55 attribute PHASE_SHIFT : string ;
56 attribute STARTUP_WAIT : string ;
57 signal CLKFB_IN : std_logic;
58 signal CLKIN_IBUFG : std_logic;
59 signal CLK0_BUF : std_logic;
60 signal CLK180_BUF : std_logic;
61 signal FDS_Q_OUT : std_logic;
62 signal FD1_Q_OUT : std_logic;
63 signal FD2_Q_OUT : std_logic;
64 signal FD3_Q_OUT : std_logic;
65 signal GND_BIT : std_logic;
66 signal OR3_O_OUT : std_logic;
67 signal RST_IN : std_logic;
68 component IBUFG
69 port ( I : in std_logic;
70 O : out std_logic);
71 end component;
72
73 component BUFG
74 port ( I : in std_logic;
75 O : out std_logic);
76 end component;
77
78 component DCM_SP
79 -- synthesis translate_off
80 generic( CLK_FEEDBACK : string := "1X";
81 CLKDV_DIVIDE : real := 2.0;
82 CLKFX_DIVIDE : integer := 1;
83 CLKFX_MULTIPLY : integer := 4;
84 CLKIN_DIVIDE_BY_2 : boolean := FALSE;
85 CLKIN_PERIOD : real := 10.0;
86 CLKOUT_PHASE_SHIFT : string := "NONE";
87 DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
88 DFS_FREQUENCY_MODE : string := "LOW";
89 DLL_FREQUENCY_MODE : string := "LOW";
90 DUTY_CYCLE_CORRECTION : boolean := TRUE;
91 FACTORY_JF : bit_vector := x"C080";
92 PHASE_SHIFT : integer := 0;
93 STARTUP_WAIT : boolean := FALSE;
94 DSS_MODE : string := "NONE");
95 -- synthesis translate_on
96 port ( CLKIN : in std_logic;
97 CLKFB : in std_logic;
98 RST : in std_logic;
99 PSEN : in std_logic;
100 PSINCDEC : in std_logic;
101 PSCLK : in std_logic;
102 DSSEN : in std_logic;
103 CLK0 : out std_logic;
104 CLK90 : out std_logic;
105 CLK180 : out std_logic;
106 CLK270 : out std_logic;
107 CLKDV : out std_logic;
108 CLK2X : out std_logic;
109 CLK2X180 : out std_logic;
110 CLKFX : out std_logic;
111 CLKFX180 : out std_logic;
112 STATUS : out std_logic_vector (7 downto 0);
113 LOCKED : out std_logic;
114 PSDONE : out std_logic);
115 end component;
116
117 component FDS
118 port ( S : in std_logic;
119 D : in std_logic;
120 C : in std_logic;
121 Q : out std_logic);
122 end component;
123
124 component FD
125 port ( D : in std_logic;
126 C : in std_logic;
127 Q : out std_logic);
128 end component;
129
130 component OR2
131 port ( I1 : in std_logic;
132 I0 : in std_logic;
133 O : out std_logic);
134 end component;
135
136 component OR3
137 port ( I2 : in std_logic;
138 I1 : in std_logic;
139 I0 : in std_logic;
140 O : out std_logic);
141 end component;
142
143 attribute CLK_FEEDBACK of DCM_SP_INST : label is "1X";
144 attribute CLKDV_DIVIDE of DCM_SP_INST : label is "2.0";
145 attribute CLKFX_DIVIDE of DCM_SP_INST : label is "1";
146 attribute CLKFX_MULTIPLY of DCM_SP_INST : label is "4";
147 attribute CLKIN_DIVIDE_BY_2 of DCM_SP_INST : label is "FALSE";
148 attribute CLKIN_PERIOD of DCM_SP_INST : label is "20.000";
149 attribute CLKOUT_PHASE_SHIFT of DCM_SP_INST : label is "FIXED";
150 attribute DESKEW_ADJUST of DCM_SP_INST : label is "SYSTEM_SYNCHRONOUS";
151 attribute DFS_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
152 attribute DLL_FREQUENCY_MODE of DCM_SP_INST : label is "LOW";
153 attribute DUTY_CYCLE_CORRECTION of DCM_SP_INST : label is "TRUE";
154 attribute FACTORY_JF of DCM_SP_INST : label is "C080";
155 attribute PHASE_SHIFT of DCM_SP_INST : label is "231";
156 attribute STARTUP_WAIT of DCM_SP_INST : label is "TRUE";
157
158-- hds translate_on
159
160begin
161
162-- hds translate_off
163
164 GND_BIT <= '0';
165 CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
166 CLK0_OUT <= CLKFB_IN;
167 CLKIN_IBUFG_INST : IBUFG
168 port map (I=>CLKIN_IN,
169 O=>CLKIN_IBUFG);
170
171 CLK0_BUFG_INST : BUFG
172 port map (I=>CLK0_BUF,
173 O=>CLKFB_IN);
174
175 CLK0_BUFG_INST1 : BUFG
176 port map (I=>CLK0_BUF,
177 O=>CLK0_OUT1);
178
179 CLK180_BUFG_INST : BUFG
180 port map (I=>CLK180_BUF,
181 O=>CLK180_OUT);
182
183 DCM_SP_INST : DCM_SP
184 -- synthesis translate_off
185 generic map( CLK_FEEDBACK => "1X",
186 CLKDV_DIVIDE => 2.0,
187 CLKFX_DIVIDE => 1,
188 CLKFX_MULTIPLY => 4,
189 CLKIN_DIVIDE_BY_2 => FALSE,
190 CLKIN_PERIOD => 20.000,
191 CLKOUT_PHASE_SHIFT => "FIXED",
192 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
193 DFS_FREQUENCY_MODE => "LOW",
194 DLL_FREQUENCY_MODE => "LOW",
195 DUTY_CYCLE_CORRECTION => TRUE,
196 FACTORY_JF => x"C080",
197 PHASE_SHIFT => 231,
198 STARTUP_WAIT => TRUE)
199 -- synthesis translate_on
200 port map (CLKFB=>CLKFB_IN,
201 CLKIN=>CLKIN_IBUFG,
202 DSSEN=>GND_BIT,
203 PSCLK=>GND_BIT,
204 PSEN=>GND_BIT,
205 PSINCDEC=>GND_BIT,
206 RST=>RST_IN,
207 CLKDV=>open,
208 CLKFX=>open,
209 CLKFX180=>open,
210 CLK0=>CLK0_BUF,
211 CLK2X=>open,
212 CLK2X180=>open,
213 CLK90=>open,
214 CLK180=>CLK180_BUF,
215 CLK270=>open,
216 LOCKED=>LOCKED_OUT,
217 PSDONE=>open,
218 STATUS=>open);
219
220 FDS_INST : FDS
221 port map (C=>CLKIN_IBUFG,
222 D=>GND_BIT,
223 S=>GND_BIT,
224 Q=>FDS_Q_OUT);
225
226 FD1_INST : FD
227 port map (C=>CLKIN_IBUFG,
228 D=>FDS_Q_OUT,
229 Q=>FD1_Q_OUT);
230
231 FD2_INST : FD
232 port map (C=>CLKIN_IBUFG,
233 D=>FD1_Q_OUT,
234 Q=>FD2_Q_OUT);
235
236 FD3_INST : FD
237 port map (C=>CLKIN_IBUFG,
238 D=>FD2_Q_OUT,
239 Q=>FD3_Q_OUT);
240
241 OR2_INST : OR2
242 port map (I0=>USER_RST_IN,
243 I1=>OR3_O_OUT,
244 O=>RST_IN);
245
246 OR3_INST : OR3
247 port map (I0=>FD3_Q_OUT,
248 I1=>FD2_Q_OUT,
249 I2=>FD1_Q_OUT,
250 O=>OR3_O_OUT);
251
252
253-- hds translate_on
254
255end BEHAVIORAL;
256
257
258
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