source: FPGA/FAD/FACT_FAD_test_devices_lib/trigger_shaper_beha.vhd@ 226

--
-- VHDL Architecture FACT_FAD_test_devices_lib.trigger_shaper.beha
--
-- Created:
--          by - FPGA_Developer.UNKNOWN (EEPC8)
--          at - 11:59:20 28.01.2010
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.NUMERIC_STD.all;

entity trigger_shaper is
  port(
    trigger_in : in std_logic;
    trigger_out : out std_logic;
    clk : in std_logic;
    rst : in std_logic
  );
end entity trigger_shaper;

architecture beha of trigger_shaper is
  
--  signal temp_trig : std_logic_vector(3 downto 0);
  signal temp_trig : std_logic_vector(1 downto 0);
  signal trigger_flag : std_logic;
  signal temp_signal : std_logic;
  
begin
  
  test_proc : process (clk, rst)
  begin
    if (rst = '1') then
      trigger_out <= '0';
      trigger_flag <= '0';
      temp_signal <= '0';
    elsif rising_edge(clk) then
--      temp_trig <= temp_trig(2 downto 0) & trigger_in;
--      trigger_out <= not temp_trig(3) and temp_trig(2);
      temp_trig <= temp_trig(0) & trigger_in;
      temp_signal <= not temp_trig(1) and temp_trig(0);
      trigger_out <= temp_signal and not trigger_flag;
      if (temp_signal = '1') then
        trigger_flag <= '1';        
      end if;
    end if;
  end process test_proc;
  
end architecture beha;