| 1 | [ModelSim]
|
|---|
| 2 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
|
|---|
| 3 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
|
|---|
| 4 | secureip = C:\FPGAdv82PS\Xilinx_Lib\secureip
|
|---|
| 5 | simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
|
|---|
| 6 | unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
|
|---|
| 7 | unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
|
|---|
| 8 | XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
|
|---|
| 9 | [QuestaSim]
|
|---|
| 10 | secureip = C:\FPGAdv82PS\Xilinx_Lib\secureip
|
|---|
| 11 | simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
|
|---|
| 12 | unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
|
|---|
| 13 | unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
|
|---|
| 14 | XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
|
|---|
| 15 | [XilinxISE]
|
|---|
| 16 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
|
|---|
| 17 | [hdl]
|
|---|
| 18 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
|
|---|
| 19 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hdl
|
|---|
| 20 | unisim = $HDS_PROJECT_DIR/unisim/hdl
|
|---|
| 21 | [hdl_vm]
|
|---|
| 22 | FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hdl_vm
|
|---|
| 23 | [hds]
|
|---|
| 24 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds
|
|---|
| 25 | FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hds
|
|---|
| 26 | unisim = $HDS_PROJECT_DIR/unisim/hds
|
|---|
| 27 | [hds_settings]
|
|---|
| 28 | default_library = FACT_FAD_lib
|
|---|
| 29 | design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd
|
|---|
| 30 | project_description = FPGA design for data acquisition from FACT
|
|---|
| 31 | version = 1
|
|---|
| 32 | [hds_vm]
|
|---|
| 33 | FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hds_vm
|
|---|
| 34 | [library_files_inclusion]
|
|---|
| 35 | FACT_FAD_lib = specify
|
|---|
| 36 | FACT_FAD_TB_lib = all
|
|---|
| 37 | [library_type]
|
|---|
| 38 | FACT_FAD_lib = regular
|
|---|
| 39 | FACT_FAD_TB_lib = regular
|
|---|
| 40 | secureip = downstream_only
|
|---|
| 41 | simprim = downstream_only
|
|---|
| 42 | unimacro = downstream_only
|
|---|
| 43 | unisim = standard
|
|---|
| 44 | XilinxCoreLib = downstream_only
|
|---|
| 45 | [protected_library_traversal]
|
|---|
| 46 | unisim = no
|
|---|
| 47 | [shared]
|
|---|
| 48 | others = $HDS_TEAM_HOME/shared.hdp
|
|---|
