source: FPGA/FAD/stable/FACT_FAD/FACT_FAD.hdp@ 3544

Last change on this file since 3544 was 252, checked in by dneise, 14 years ago
DRS addresses may not be set via sa 44 0 .. 31
File size: 1.7 KB
Line 
1[DesignChecker]
2FACT_FAD_lib = $HDS_PROJECT_DIR\FACT_FAD_lib\designcheck
3[ModelSim]
4FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
5FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/work
6secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip
7simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
8unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
9unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
10XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
11[QuestaSim]
12secureip = C:/FPGAdv82PS/Xilinx_Lib/secureip
13simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
14unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
15unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
16XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
17[XilinxISE]
18FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
19[hdl]
20FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
21FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hdl
22unisim = $HDS_PROJECT_DIR/unisim/hdl
23[hdl_vm]
24FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hdl_vm
25[hds]
26FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds
27FACT_FAD_TB_lib = $HDS_PROJECT_DIR/FACT_FAD_TB_lib/hds
28unisim = $HDS_PROJECT_DIR/unisim/hds
29[hds_settings]
30default_library = FACT_FAD_lib
31design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd
32project_description = FPGA design for data acquisition from FACT
33version = 1
34[hds_vm]
35FACT_FAD_TB_lib = $HDS_HOME/examples/hds_scratch/hds_repository/FACT_FAD_TB_lib/hds_vm
36[library_files_inclusion]
37FACT_FAD_lib = specify
38FACT_FAD_TB_lib = all
39[library_type]
40FACT_FAD_lib = regular
41FACT_FAD_TB_lib = regular
42secureip = downstream_only
43simprim = downstream_only
44unimacro = downstream_only
45unisim = standard
46XilinxCoreLib = downstream_only
47[protected_library_traversal]
48unisim = no
49[shared]
50others = $HDS_TEAM_HOME/shared.hdp
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