source: FPGA/FAD/stable/FACT_FAD/FACT_FAD_lib/hds/@f@a@d_main/struct.bd@ 246

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "IEEE"
unitName "STD_LOGIC_ARITH"
)
(DmPackageRef
library "ieee"
unitName "STD_LOGIC_UNSIGNED"
)
(DmPackageRef
library "fact_fad_lib"
unitName "fad_definitions"
)
(DmPackageRef
library "UNISIM"
unitName "VComponents"
)
(DmPackageRef
library "IEEE"
unitName "NUMERIC_STD"
)
(DmPackageRef
library "IEEE"
unitName "std_logic_signed"
)
]
instances [
(Instance
name "I_main_data_generator"
duLibraryName "FACT_FAD_lib"
duName "data_generator"
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b"
)
]
mwi 0
uid 1399,0
)
(Instance
name "I_main_ethernet"
duLibraryName "FACT_FAD_lib"
duName "w5300_modul"
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
mwi 0
uid 1606,0
)
(Instance
name "I_main_ext_trigger"
duLibraryName "FACT_FAD_LIB"
duName "trigger_counter"
elements [
]
mwi 0
uid 1768,0
)
(Instance
name "I_main_memory_manager"
duLibraryName "FACT_FAD_lib"
duName "memory_manager"
elements [
(GiElement
name "RAM_ADDR_WIDTH_64B"
type "integer"
value "RAMADDRWIDTH64b"
)
(GiElement
name "RAM_ADDR_WIDTH_16B"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
mwi 0
uid 2311,0
)
(Instance
name "I_main_clock_gen"
duLibraryName "FACT_FAD_lib"
duName "clock_generator"
elements [
]
mwi 0
uid 4194,0
)
(Instance
name "I_main_drs_pulser"
duLibraryName "FACT_FAD_LIB"
duName "drs_pulser"
elements [
]
mwi 0
uid 4903,0
)
(Instance
name "I_main_control_unit"
duLibraryName "FACT_FAD_lib"
duName "control_unit"
elements [
]
mwi 0
uid 5072,0
)
(Instance
name "I_main_adc_buffer"
duLibraryName "FACT_FAD_lib"
duName "adc_buffer"
elements [
]
mwi 0
uid 5678,0
)
(Instance
name "I_main_SPI_interface"
duLibraryName "FACT_FAD_lib"
duName "spi_interface"
elements [
]
mwi 0
uid 5793,0
)
(Instance
name "I5"
duLibraryName "moduleware"
duName "and"
elements [
]
mwi 1
uid 6529,0
)
(Instance
name "U_4"
duLibraryName "FACT_FAD_lib"
duName "dataRAM_64b_16b_width14_5"
elements [
]
mwi 0
uid 8277,0
)
]
libraryRefs [
"ieee"
"fact_fad_lib"
"UNISIM"
]
)
version "29.1"
appVersion "2009.2 (Build 10)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable "HDLDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main"
)
(vvPair
variable "d_logical"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main"
)
(vvPair
variable "date"
value "02.07.2010"
)
(vvPair
variable "day"
value "Fr"
)
(vvPair
variable "day_long"
value "Freitag"
)
(vvPair
variable "dd"
value "02"
)
(vvPair
variable "entity_name"
value "FAD_main"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "TU-CC4900F8C7D2"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "FACT_FAD_lib"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/designcheck"
)
(vvPair
variable "library_downstream_ISEPARInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ImpactInvoke"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/work"
)
(vvPair
variable "library_downstream_PrecisionSynthesisDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ps"
)
(vvPair
variable "library_downstream_XSTDataPrep"
value "$HDS_PROJECT_DIR/FACT_FAD_lib/ise"
)
(vvPair
variable "mm"
value "07"
)
(vvPair
variable "module_name"
value "FAD_main"
)
(vvPair
variable "month"
value "Jul"
)
(vvPair
variable "month_long"
value "Juli"
)
(vvPair
variable "p"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\@f@a@d_main\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\FPGA_projects\\FACT_FAD_02072010\\FACT_FAD\\FACT_FAD_lib\\hds\\FAD_main\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "FACT_FAD"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "<TBD>"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "10:38:34"
)
(vvPair
variable "unit"
value "FAD_main"
)
(vvPair
variable "user"
value "dneise"
)
(vvPair
variable "version"
value "2009.2 (Build 10)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2010"
)
(vvPair
variable "yy"
value "10"
)
]
)
LanguageMgr "VhdlLangMgr"
uid 52,0
optionalChildren [
*1 (PortIoIn
uid 290,0
shape (CompositeShape
uid 291,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 292,0
sl 0
ro 270
xt "-28000,18625,-26500,19375"
)
(Line
uid 293,0
sl 0
ro 270
xt "-26500,19000,-26000,19000"
pts [
"-26500,19000"
"-26000,19000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 294,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 295,0
va (VaSet
)
xt "-30900,18500,-29000,19500"
st "CLK"
ju 2
blo "-29000,19300"
tm "WireNameMgr"
)
)
)
*2 (Net
uid 320,0
decl (Decl
n "write_ea"
t "std_logic_vector"
b "(0 downto 0)"
o 80
suid 2,0
i "\"0\""
)
declText (MLText
uid 321,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,84200,-41500,85000"
st "SIGNAL write_ea               : std_logic_vector(0 downto 0)                 := \"0\""
)
)
*3 (Net
uid 326,0
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAMADDRWIDTH64b-1 DOWNTO 0)"
o 35
suid 3,0
)
declText (MLText
uid 327,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,47400,-45000,48200"
st "SIGNAL addr_out               : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
)
)
*4 (Net
uid 332,0
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 DOWNTO 0)"
o 53
suid 4,0
)
declText (MLText
uid 333,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,61800,-52500,62600"
st "SIGNAL data_out               : std_logic_vector(63 DOWNTO 0)"
)
)
*5 (Net
uid 362,0
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b+1 DOWNTO 0)"
o 62
suid 9,0
)
declText (MLText
uid 363,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,69000,-45000,69800"
st "SIGNAL ram_addr               : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0)"
)
)
*6 (Net
uid 368,0
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 downto 0)"
o 63
suid 10,0
)
declText (MLText
uid 369,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,69800,-52500,70600"
st "SIGNAL ram_data               : std_logic_vector(15 downto 0)"
)
)
*7 (Net
uid 374,0
decl (Decl
n "wiz_reset"
t "std_logic"
o 28
suid 11,0
i "'1'"
)
declText (MLText
uid 375,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,39800,-45000,40600"
st "wiz_reset              : std_logic                                    := '1'"
)
)
*8 (Net
uid 382,0
decl (Decl
n "wiz_addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
o 25
suid 12,0
)
declText (MLText
uid 383,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,37400,-56500,38200"
st "wiz_addr               : std_logic_vector(9 DOWNTO 0)"
)
)
*9 (Net
uid 390,0
decl (Decl
n "wiz_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 31
suid 13,0
)
declText (MLText
uid 391,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,42200,-56000,43000"
st "wiz_data               : std_logic_vector(15 DOWNTO 0)"
)
)
*10 (Net
uid 398,0
decl (Decl
n "wiz_cs"
t "std_logic"
o 26
suid 14,0
i "'1'"
)
declText (MLText
uid 399,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,38200,-45000,39000"
st "wiz_cs                 : std_logic                                    := '1'"
)
)
*11 (Net
uid 406,0
decl (Decl
n "wiz_wr"
t "std_logic"
o 29
suid 15,0
i "'1'"
)
declText (MLText
uid 407,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,40600,-45000,41400"
st "wiz_wr                 : std_logic                                    := '1'"
)
)
*12 (Net
uid 422,0
decl (Decl
n "wiz_rd"
t "std_logic"
o 27
suid 17,0
i "'1'"
)
declText (MLText
uid 423,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,39000,-45000,39800"
st "wiz_rd                 : std_logic                                    := '1'"
)
)
*13 (Net
uid 430,0
decl (Decl
n "wiz_int"
t "std_logic"
o 11
suid 18,0
)
declText (MLText
uid 431,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,26200,-66500,27000"
st "wiz_int                : std_logic"
)
)
*14 (PortIoOut
uid 454,0
shape (CompositeShape
uid 455,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 456,0
sl 0
ro 270
xt "153500,51625,155000,52375"
)
(Line
uid 457,0
sl 0
ro 270
xt "153000,52000,153500,52000"
pts [
"153000,52000"
"153500,52000"
]
)
]
)
sf 1
tg (WTG
uid 458,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 459,0
va (VaSet
)
xt "156000,51500,159600,52500"
st "wiz_reset"
blo "156000,52300"
tm "WireNameMgr"
)
)
)
*15 (PortIoOut
uid 460,0
shape (CompositeShape
uid 461,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 462,0
sl 0
ro 270
xt "153500,59625,155000,60375"
)
(Line
uid 463,0
sl 0
ro 270
xt "153000,60000,153500,60000"
pts [
"153000,60000"
"153500,60000"
]
)
]
)
sf 1
tg (WTG
uid 464,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 465,0
va (VaSet
)
xt "156000,59500,162000,60500"
st "wiz_addr : (9:0)"
blo "156000,60300"
tm "WireNameMgr"
)
)
)
*16 (PortIoInOut
uid 466,0
shape (CompositeShape
uid 467,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
uid 468,0
sl 0
xt "153500,60625,155000,61375"
)
(Line
uid 469,0
sl 0
xt "153000,61000,153500,61000"
pts [
"153000,61000"
"153500,61000"
]
)
]
)
sf 1
tg (WTG
uid 470,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 471,0
va (VaSet
)
xt "156000,60500,162300,61500"
st "wiz_data : (15:0)"
blo "156000,61300"
tm "WireNameMgr"
)
)
)
*17 (PortIoOut
uid 472,0
shape (CompositeShape
uid 473,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 474,0
sl 0
ro 270
xt "153500,52625,155000,53375"
)
(Line
uid 475,0
sl 0
ro 270
xt "153000,53000,153500,53000"
pts [
"153000,53000"
"153500,53000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 476,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 477,0
va (VaSet
)
xt "156000,52500,158700,53500"
st "wiz_cs"
blo "156000,53300"
tm "WireNameMgr"
)
)
)
*18 (PortIoOut
uid 478,0
shape (CompositeShape
uid 479,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 480,0
sl 0
ro 270
xt "153500,53625,155000,54375"
)
(Line
uid 481,0
sl 0
ro 270
xt "153000,54000,153500,54000"
pts [
"153000,54000"
"153500,54000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 482,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 483,0
va (VaSet
)
xt "156000,53500,158700,54500"
st "wiz_wr"
blo "156000,54300"
tm "WireNameMgr"
)
)
)
*19 (PortIoOut
uid 484,0
shape (CompositeShape
uid 485,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 486,0
sl 0
ro 270
xt "153500,70625,155000,71375"
)
(Line
uid 487,0
sl 0
ro 270
xt "153000,71000,153500,71000"
pts [
"153000,71000"
"153500,71000"
]
)
]
)
sf 1
tg (WTG
uid 488,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 489,0
va (VaSet
)
xt "156000,70500,160000,71500"
st "led : (7:0)"
blo "156000,71300"
tm "WireNameMgr"
)
)
)
*20 (PortIoOut
uid 490,0
shape (CompositeShape
uid 491,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 492,0
sl 0
ro 270
xt "153500,54625,155000,55375"
)
(Line
uid 493,0
sl 0
ro 270
xt "153000,55000,153500,55000"
pts [
"153000,55000"
"153500,55000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 494,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 495,0
va (VaSet
)
xt "156000,54500,158600,55500"
st "wiz_rd"
blo "156000,55300"
tm "WireNameMgr"
)
)
)
*21 (PortIoIn
uid 496,0
shape (CompositeShape
uid 497,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 498,0
sl 0
ro 90
xt "153500,55625,155000,56375"
)
(Line
uid 499,0
sl 0
ro 90
xt "153000,56000,153500,56000"
pts [
"153500,56000"
"153000,56000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 500,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 501,0
va (VaSet
)
xt "156000,55500,158700,56500"
st "wiz_int"
blo "156000,56300"
tm "WireNameMgr"
)
)
)
*22 (SaComponent
uid 1399,0
optionalChildren [
*23 (CptPort
uid 1352,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1353,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,47625,19000,48375"
)
tg (CPTG
uid 1354,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1355,0
va (VaSet
)
xt "20000,47500,21300,48500"
st "clk"
blo "20000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*24 (CptPort
uid 1356,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1357,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,49625,40750,50375"
)
tg (CPTG
uid 1358,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1359,0
va (VaSet
)
xt "32800,49500,39000,50500"
st "data_out : (63:0)"
ju 2
blo "39000,50300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_out"
t "std_logic_vector"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*25 (CptPort
uid 1360,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1361,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,48625,40750,49375"
)
tg (CPTG
uid 1362,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1363,0
va (VaSet
)
xt "24900,48500,39000,49500"
st "addr_out : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "39000,49300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr_out"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*26 (CptPort
uid 1372,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1373,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,47625,40750,48375"
)
tg (CPTG
uid 1374,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1375,0
va (VaSet
)
xt "33200,47500,39000,48500"
st "write_ea : (0:0)"
ju 2
blo "39000,48300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "write_ea"
t "std_logic_vector"
b "(0 downto 0)"
preAdd 0
posAdd 0
o 4
suid 6,0
i "\"0\""
)
)
)
*27 (CptPort
uid 1376,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2344,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,62625,40750,63375"
)
tg (CPTG
uid 1378,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1379,0
va (VaSet
)
xt "22700,62500,39000,63500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
ju 2
blo "39000,63300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 downto 0)"
preAdd 0
posAdd 0
o 5
suid 7,0
)
)
)
*28 (CptPort
uid 1384,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1385,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,85625,19000,86375"
)
tg (CPTG
uid 1386,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1387,0
va (VaSet
)
xt "20000,85500,25900,86500"
st "board_id : (3:0)"
blo "20000,86300"
)
)
thePort (LogicalPort
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 23
suid 9,0
)
)
)
*29 (CptPort
uid 1388,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1389,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,67625,19000,68375"
)
tg (CPTG
uid 1390,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1391,0
va (VaSet
)
xt "20000,67500,26800,68500"
st "trigger_id : (47:0)"
blo "20000,68300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 25
suid 10,0
)
)
)
*30 (CptPort
uid 1392,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1393,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,68625,19000,69375"
)
tg (CPTG
uid 1394,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1395,0
va (VaSet
)
xt "20000,68500,22800,69500"
st "trigger"
blo "20000,69300"
)
)
thePort (LogicalPort
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 26
suid 11,0
)
)
)
*31 (CptPort
uid 1676,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1677,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,86625,19000,87375"
)
tg (CPTG
uid 1678,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1679,0
va (VaSet
)
xt "20000,86500,25700,87500"
st "crate_id : (1:0)"
blo "20000,87300"
)
)
thePort (LogicalPort
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 24
suid 12,0
)
)
)
*32 (CptPort
uid 2562,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2563,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,63625,40750,64375"
)
tg (CPTG
uid 2564,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2565,0
va (VaSet
)
xt "33700,63500,39000,64500"
st "ram_write_ea"
ju 2
blo "39000,64300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_write_ea"
t "std_logic"
o 6
suid 16,0
)
)
)
*33 (CptPort
uid 2566,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2567,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,64625,40750,65375"
)
tg (CPTG
uid 2568,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2569,0
va (VaSet
)
xt "32700,64500,39000,65500"
st "ram_write_ready"
ju 2
blo "39000,65300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_write_ready"
t "std_logic"
o 7
suid 17,0
i "'0'"
)
)
)
*34 (CptPort
uid 2570,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2571,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,73625,40750,74375"
)
tg (CPTG
uid 2572,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2573,0
va (VaSet
)
xt "36000,73500,39000,74500"
st "roi_max"
ju 2
blo "39000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "roi_max"
t "roi_max_type"
o 18
suid 18,0
)
)
)
*35 (CptPort
uid 2614,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2615,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,79625,40750,80375"
)
tg (CPTG
uid 2616,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2617,0
va (VaSet
)
xt "35600,79500,39000,80500"
st "roi_array"
ju 2
blo "39000,80300"
)
)
thePort (LogicalPort
decl (Decl
n "roi_array"
t "roi_array_type"
o 17
suid 19,0
)
)
)
*36 (CptPort
uid 2624,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2625,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,74625,40750,75375"
)
tg (CPTG
uid 2626,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2627,0
va (VaSet
)
xt "29900,74500,39000,75500"
st "package_length : (15:0)"
ju 2
blo "39000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 22
suid 20,0
)
)
)
*37 (CptPort
uid 2760,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2761,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,81625,19000,82375"
)
tg (CPTG
uid 2762,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2763,0
va (VaSet
)
xt "20000,81500,23200,82500"
st "adc_oeb"
blo "20000,82300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_oeb"
t "std_logic"
o 31
suid 23,0
i "'1'"
)
)
)
*38 (CptPort
uid 2764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2765,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,76625,19000,77375"
)
tg (CPTG
uid 2766,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2767,0
va (VaSet
)
xt "20000,76500,25500,77500"
st "adc_otr : (3:0)"
blo "20000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 downto 0)"
o 32
suid 24,0
)
)
)
*39 (CptPort
uid 3918,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3919,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,56625,19000,57375"
)
tg (CPTG
uid 3920,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3921,0
va (VaSet
)
xt "20000,56500,28500,57500"
st "drs_channel_id : (3:0)"
blo "20000,57300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 33
suid 25,0
i "(others => '0')"
)
)
)
*40 (CptPort
uid 3922,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3923,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,52625,19000,53375"
)
tg (CPTG
uid 3924,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3925,0
va (VaSet
)
xt "20000,52500,24400,53500"
st "drs_clk_en"
blo "20000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_clk_en"
t "std_logic"
o 35
suid 26,0
i "'0'"
)
)
)
*41 (CptPort
uid 3926,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3927,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,58625,19000,59375"
)
tg (CPTG
uid 3928,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3929,0
va (VaSet
)
xt "20000,58500,24300,59500"
st "drs_dwrite"
blo "20000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_dwrite"
t "std_logic"
o 34
suid 36,0
i "'1'"
)
)
)
*42 (CptPort
uid 3930,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3931,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,49625,19000,50375"
)
tg (CPTG
uid 3932,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3933,0
va (VaSet
)
xt "20000,49500,26200,50500"
st "drs_read_s_cell"
blo "20000,50300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "drs_read_s_cell"
t "std_logic"
o 36
suid 33,0
i "'0'"
)
)
)
*43 (CptPort
uid 3934,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3935,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,50625,19000,51375"
)
tg (CPTG
uid 3936,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3937,0
va (VaSet
)
xt "20000,50500,28800,51500"
st "drs_read_s_cell_ready"
blo "20000,51300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 37
suid 34,0
)
)
)
*44 (CptPort
uid 3938,0
ps "OnEdgeStrategy"
shape (Triangle
uid 3939,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,51625,19000,52375"
)
tg (CPTG
uid 3940,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 3941,0
va (VaSet
)
xt "20000,51500,26400,52500"
st "drs_s_cell_array"
blo "20000,52300"
)
)
thePort (LogicalPort
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 38
suid 35,0
)
)
)
*45 (CptPort
uid 4246,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4247,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "18250,75625,19000,76375"
)
tg (CPTG
uid 4248,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4249,0
va (VaSet
)
xt "20000,75500,25900,76500"
st "adc_data_array"
blo "20000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 30
suid 37,0
)
)
)
*46 (CptPort
uid 5174,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5175,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,82625,40750,83375"
)
tg (CPTG
uid 5176,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5177,0
va (VaSet
)
xt "32500,82500,39000,83500"
st "config_ready_cm"
ju 2
blo "39000,83300"
)
)
thePort (LogicalPort
decl (Decl
n "config_ready_cm"
t "std_logic"
o 12
suid 39,0
)
)
)
*47 (CptPort
uid 5178,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5179,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,80625,40750,81375"
)
tg (CPTG
uid 5180,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5181,0
va (VaSet
)
xt "32800,80500,39000,81500"
st "config_start_cm"
ju 2
blo "39000,81300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_cm"
t "std_logic"
o 9
suid 40,0
i "'0'"
)
)
)
*48 (CptPort
uid 5271,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5272,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,52625,40750,53375"
)
tg (CPTG
uid 5273,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5274,0
va (VaSet
)
xt "35400,52500,39000,53500"
st "s_trigger"
ju 2
blo "39000,53300"
)
)
thePort (LogicalPort
decl (Decl
n "s_trigger"
t "std_logic"
o 27
suid 41,0
)
)
)
*49 (CptPort
uid 5392,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5393,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,71625,40750,72375"
)
tg (CPTG
uid 5394,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5395,0
va (VaSet
)
xt "32300,71500,39000,72500"
st "config_ready_mm"
ju 2
blo "39000,72300"
)
)
thePort (LogicalPort
decl (Decl
n "config_ready_mm"
t "std_logic"
o 11
suid 42,0
)
)
)
*50 (CptPort
uid 5396,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5397,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,84625,40750,85375"
)
tg (CPTG
uid 5398,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5399,0
va (VaSet
)
xt "32500,84500,39000,85500"
st "config_ready_spi"
ju 2
blo "39000,85300"
)
)
thePort (LogicalPort
decl (Decl
n "config_ready_spi"
t "std_logic"
o 13
suid 43,0
)
)
)
*51 (CptPort
uid 5464,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5465,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,88625,40750,89375"
)
tg (CPTG
uid 5466,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5467,0
va (VaSet
)
xt "33800,88500,39000,89500"
st "sensor_array"
ju 2
blo "39000,89300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 19
suid 44,0
)
)
)
*52 (CptPort
uid 5468,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5469,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,89625,40750,90375"
)
tg (CPTG
uid 5470,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5471,0
va (VaSet
)
xt "33700,89500,39000,90500"
st "sensor_ready"
ju 2
blo "39000,90300"
)
)
thePort (LogicalPort
decl (Decl
n "sensor_ready"
t "std_logic"
o 20
suid 45,0
)
)
)
*53 (CptPort
uid 5735,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5736,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,69625,40750,70375"
)
tg (CPTG
uid 5737,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5738,0
va (VaSet
)
xt "32600,69500,39000,70500"
st "config_start_mm"
ju 2
blo "39000,70300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_mm"
t "std_logic"
o 8
suid 46,0
i "'0'"
)
)
)
*54 (CptPort
uid 5739,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5740,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,86625,40750,87375"
)
tg (CPTG
uid 5741,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5742,0
va (VaSet
)
xt "32800,86500,39000,87500"
st "config_start_spi"
ju 2
blo "39000,87300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_start_spi"
t "std_logic"
o 10
suid 47,0
i "'0'"
)
)
)
*55 (CptPort
uid 5916,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5917,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,54625,40750,55375"
)
tg (CPTG
uid 5918,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5919,0
va (VaSet
)
xt "33400,54500,39000,55500"
st "config_started"
ju 2
blo "39000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 29
suid 48,0
i "'0'"
)
)
)
*56 (CptPort
uid 5920,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5921,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,53625,40750,54375"
)
tg (CPTG
uid 5922,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5923,0
va (VaSet
)
xt "34400,53500,39000,54500"
st "new_config"
ju 2
blo "39000,54300"
)
)
thePort (LogicalPort
decl (Decl
n "new_config"
t "std_logic"
o 28
suid 49,0
)
)
)
*57 (CptPort
uid 5974,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5975,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,81625,40750,82375"
)
tg (CPTG
uid 5976,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5977,0
va (VaSet
)
xt "32000,81500,39000,82500"
st "config_started_cm"
ju 2
blo "39000,82300"
)
)
thePort (LogicalPort
decl (Decl
n "config_started_cm"
t "std_logic"
o 15
suid 50,0
)
)
)
*58 (CptPort
uid 5978,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5979,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,70625,40750,71375"
)
tg (CPTG
uid 5980,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5981,0
va (VaSet
)
xt "31800,70500,39000,71500"
st "config_started_mm"
ju 2
blo "39000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "config_started_mm"
t "std_logic"
o 14
suid 51,0
)
)
)
*59 (CptPort
uid 5982,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5983,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,85625,40750,86375"
)
tg (CPTG
uid 5984,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5985,0
va (VaSet
)
xt "32000,85500,39000,86500"
st "config_started_spi"
ju 2
blo "39000,86300"
)
)
thePort (LogicalPort
decl (Decl
n "config_started_spi"
t "std_logic"
o 16
suid 52,0
)
)
)
*60 (CptPort
uid 6060,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6061,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "40000,78625,40750,79375"
)
tg (CPTG
uid 6062,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6063,0
va (VaSet
)
xt "35300,78500,39000,79500"
st "dac_array"
ju 2
blo "39000,79300"
)
)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
o 21
suid 53,0
)
)
)
]
shape (Rectangle
uid 1400,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "19000,47000,40000,91000"
)
oxt "37000,1000,51000,21000"
ttg (MlTextGroup
uid 1401,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*61 (Text
uid 1402,0
va (VaSet
font "Arial,8,1"
)
xt "19300,91000,25500,92000"
st "FACT_FAD_lib"
blo "19300,91800"
tm "BdLibraryNameMgr"
)
*62 (Text
uid 1403,0
va (VaSet
font "Arial,8,1"
)
xt "19300,92000,25700,93000"
st "data_generator"
blo "19300,92800"
tm "CptNameMgr"
)
*63 (Text
uid 1404,0
va (VaSet
font "Arial,8,1"
)
xt "19300,93000,28900,94000"
st "I_main_data_generator"
blo "19300,93800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1405,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1406,0
text (MLText
uid 1407,0
va (VaSet
font "Courier New,8,0"
)
xt "19000,46200,45500,47000"
st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b"
)
]
)
viewicon (ZoomableIcon
uid 1408,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "19250,89250,20750,90750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*64 (Net
uid 1409,0
decl (Decl
n "board_id"
t "std_logic_vector"
b "(3 downto 0)"
preAdd 0
posAdd 0
o 8
suid 28,0
)
declText (MLText
uid 1410,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,23800,-56500,24600"
st "board_id               : std_logic_vector(3 downto 0)"
)
)
*65 (Net
uid 1423,0
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 10
suid 29,0
)
declText (MLText
uid 1424,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,25400,-66500,26200"
st "trigger                : std_logic"
)
)
*66 (PortIoIn
uid 1443,0
shape (CompositeShape
uid 1444,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 1445,0
sl 0
ro 270
xt "-28000,68625,-26500,69375"
)
(Line
uid 1446,0
sl 0
ro 270
xt "-26500,69000,-26000,69000"
pts [
"-26500,69000"
"-26000,69000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 1447,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1448,0
va (VaSet
)
xt "-31800,68500,-29000,69500"
st "trigger"
ju 2
blo "-29000,69300"
tm "WireNameMgr"
)
)
)
*67 (SaComponent
uid 1606,0
optionalChildren [
*68 (CptPort
uid 1542,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1543,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,51625,127000,52375"
)
tg (CPTG
uid 1544,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1545,0
va (VaSet
)
xt "128000,51500,129300,52500"
st "clk"
blo "128000,52300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*69 (CptPort
uid 1546,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1547,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,51625,148750,52375"
)
tg (CPTG
uid 1548,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1549,0
va (VaSet
)
xt "143400,51500,147000,52500"
st "wiz_reset"
ju 2
blo "147000,52300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wiz_reset"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
i "'1'"
)
)
)
*70 (CptPort
uid 1550,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1551,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,59625,148750,60375"
)
tg (CPTG
uid 1552,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1553,0
va (VaSet
)
xt "142500,59500,147000,60500"
st "addr : (9:0)"
ju 2
blo "147000,60300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "addr"
t "std_logic_vector"
b "(9 DOWNTO 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*71 (CptPort
uid 1554,0
ps "OnEdgeStrategy"
shape (Diamond
uid 1555,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,60625,148750,61375"
)
tg (CPTG
uid 1556,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1557,0
va (VaSet
)
xt "142200,60500,147000,61500"
st "data : (15:0)"
ju 2
blo "147000,61300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 4
suid 4,0
)
)
)
*72 (CptPort
uid 1558,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1559,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,52625,148750,53375"
)
tg (CPTG
uid 1560,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1561,0
va (VaSet
)
xt "145800,52500,147000,53500"
st "cs"
ju 2
blo "147000,53300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "cs"
t "std_logic"
preAdd 0
posAdd 0
o 5
suid 5,0
i "'1'"
)
)
)
*73 (CptPort
uid 1562,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1563,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,53625,148750,54375"
)
tg (CPTG
uid 1564,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1565,0
va (VaSet
)
xt "145800,53500,147000,54500"
st "wr"
ju 2
blo "147000,54300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "wr"
t "std_logic"
preAdd 0
posAdd 0
o 6
suid 6,0
i "'1'"
)
)
)
*74 (CptPort
uid 1570,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1571,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,54625,148750,55375"
)
tg (CPTG
uid 1572,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1573,0
va (VaSet
)
xt "145900,54500,147000,55500"
st "rd"
ju 2
blo "147000,55300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "rd"
t "std_logic"
preAdd 0
posAdd 0
o 8
suid 8,0
i "'1'"
)
)
)
*75 (CptPort
uid 1574,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1575,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,55625,148750,56375"
)
tg (CPTG
uid 1576,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1577,0
va (VaSet
)
xt "145800,55500,147000,56500"
st "int"
ju 2
blo "147000,56300"
)
)
thePort (LogicalPort
decl (Decl
n "int"
t "std_logic"
preAdd 0
posAdd 0
o 9
suid 9,0
)
)
)
*76 (CptPort
uid 1578,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1579,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,69625,127000,70375"
)
tg (CPTG
uid 1580,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1581,0
va (VaSet
)
xt "128000,69500,135900,70500"
st "write_length : (16:0)"
blo "128000,70300"
)
)
thePort (LogicalPort
decl (Decl
n "write_length"
t "std_logic_vector"
b "(16 DOWNTO 0)"
preAdd 0
posAdd 0
o 10
suid 10,0
)
)
)
*77 (CptPort
uid 1582,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1583,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,70625,127000,71375"
)
tg (CPTG
uid 1584,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1585,0
va (VaSet
)
xt "128000,70500,144300,71500"
st "ram_start_addr : (RAM_ADDR_WIDTH-1:0)"
blo "128000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 11
suid 11,0
)
)
)
*78 (CptPort
uid 1586,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1587,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,54625,127000,55375"
)
tg (CPTG
uid 1588,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1589,0
va (VaSet
)
xt "128000,54500,134500,55500"
st "ram_data : (15:0)"
blo "128000,55300"
)
)
thePort (LogicalPort
decl (Decl
n "ram_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
preAdd 0
posAdd 0
o 12
suid 12,0
)
)
)
*79 (CptPort
uid 1590,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1591,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,53625,127000,54375"
)
tg (CPTG
uid 1592,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1593,0
va (VaSet
)
xt "128000,53500,142400,54500"
st "ram_addr : (RAM_ADDR_WIDTH-1:0)"
blo "128000,54300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ram_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 13
suid 13,0
)
)
)
*80 (CptPort
uid 1594,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1595,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,68625,127000,69375"
)
tg (CPTG
uid 1596,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1597,0
va (VaSet
)
xt "128000,68500,132100,69500"
st "data_valid"
blo "128000,69300"
)
)
thePort (LogicalPort
decl (Decl
n "data_valid"
t "std_logic"
preAdd 0
posAdd 0
o 14
suid 14,0
)
)
)
*81 (CptPort
uid 1598,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1599,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,67625,127000,68375"
)
tg (CPTG
uid 1600,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1601,0
va (VaSet
)
xt "128000,67500,129900,68500"
st "busy"
blo "128000,68300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "busy"
t "std_logic"
preAdd 0
posAdd 0
o 16
suid 15,0
i "'1'"
)
)
)
*82 (CptPort
uid 2218,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2219,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,71625,127000,72375"
)
tg (CPTG
uid 2220,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2221,0
va (VaSet
)
xt "128000,71500,135800,72500"
st "fifo_channels : (3:0)"
blo "128000,72300"
)
)
thePort (LogicalPort
decl (Decl
n "fifo_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 19
suid 20,0
)
)
)
*83 (CptPort
uid 2222,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2223,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,72625,127000,73375"
)
tg (CPTG
uid 2224,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2225,0
va (VaSet
)
xt "128000,72500,133700,73500"
st "write_end_flag"
blo "128000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "write_end_flag"
t "std_logic"
o 18
suid 18,0
)
)
)
*84 (CptPort
uid 2226,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2227,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,73625,127000,74375"
)
tg (CPTG
uid 2228,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2229,0
va (VaSet
)
xt "128000,73500,134800,74500"
st "write_header_flag"
blo "128000,74300"
)
)
thePort (LogicalPort
decl (Decl
n "write_header_flag"
t "std_logic"
o 17
suid 19,0
)
)
)
*85 (CptPort
uid 5216,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5217,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,70625,148750,71375"
)
tg (CPTG
uid 5218,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5219,0
va (VaSet
)
xt "143000,70500,147000,71500"
st "led : (7:0)"
ju 2
blo "147000,71300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 7
suid 22,0
i "(OTHERS => '0')"
)
)
)
*86 (CptPort
uid 5275,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5276,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,58625,127000,59375"
)
tg (CPTG
uid 5277,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5278,0
va (VaSet
)
xt "128000,58500,131600,59500"
st "s_trigger"
blo "128000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "s_trigger"
t "std_logic"
o 20
suid 23,0
i "'0'"
)
)
)
*87 (CptPort
uid 5924,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5925,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,78625,127000,79375"
)
tg (CPTG
uid 5926,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5927,0
va (VaSet
)
xt "128000,78500,135000,79500"
st "config_addr : (7:0)"
blo "128000,79300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(7 downto 0)"
o 23
suid 24,0
)
)
)
*88 (CptPort
uid 5928,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5929,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,83625,127000,84375"
)
tg (CPTG
uid 5930,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5931,0
va (VaSet
)
xt "128000,83500,132800,84500"
st "config_busy"
blo "128000,84300"
)
)
thePort (LogicalPort
decl (Decl
n "config_busy"
t "std_logic"
o 27
suid 25,0
)
)
)
*89 (CptPort
uid 5932,0
ps "OnEdgeStrategy"
shape (Diamond
uid 6051,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,79625,127000,80375"
)
tg (CPTG
uid 5934,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5935,0
va (VaSet
)
xt "128000,79500,135700,80500"
st "config_data : (15:0)"
blo "128000,80300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "config_data"
t "std_logic_vector"
b "(15 downto 0)"
o 24
suid 26,0
i "(others => 'Z')"
)
)
)
*90 (CptPort
uid 5936,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5937,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,60625,127000,61375"
)
tg (CPTG
uid 5938,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5939,0
va (VaSet
)
xt "128000,60500,133600,61500"
st "config_started"
blo "128000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "config_started"
t "std_logic"
o 22
suid 27,0
)
)
)
*91 (CptPort
uid 5940,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5941,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,81625,127000,82375"
)
tg (CPTG
uid 5942,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5943,0
va (VaSet
)
xt "128000,81500,133300,82500"
st "config_wr_en"
blo "128000,82300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_wr_en"
t "std_logic"
o 25
suid 28,0
i "'0'"
)
)
)
*92 (CptPort
uid 5944,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5945,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,59625,127000,60375"
)
tg (CPTG
uid 5946,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5947,0
va (VaSet
)
xt "128000,59500,132600,60500"
st "new_config"
blo "128000,60300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "new_config"
t "std_logic"
o 21
suid 29,0
i "'0'"
)
)
)
*93 (CptPort
uid 5970,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5971,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,82625,127000,83375"
)
tg (CPTG
uid 5972,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5973,0
va (VaSet
)
xt "128000,82500,133200,83500"
st "config_rd_en"
blo "128000,83300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_rd_en"
t "std_logic"
o 26
suid 30,0
i "'0'"
)
)
)
*94 (CptPort
uid 6356,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6357,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,74625,148750,75375"
)
tg (CPTG
uid 6358,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6359,0
va (VaSet
)
xt "144000,74500,147000,75500"
st "denable"
ju 2
blo "147000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 28
suid 31,0
i "'0'"
)
)
)
*95 (CptPort
uid 6446,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6447,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "148000,75625,148750,76375"
)
tg (CPTG
uid 6448,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6449,0
va (VaSet
)
xt "141600,75500,147000,76500"
st "dwrite_enable"
ju 2
blo "147000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dwrite_enable"
t "std_logic"
eolc "-- default DWRITE low."
preAdd 0
posAdd 0
o 29
suid 32,0
i "'0'"
)
)
)
*96 (CptPort
uid 8406,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8407,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "126250,74625,127000,75375"
)
tg (CPTG
uid 8408,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8409,0
va (VaSet
)
xt "128000,74500,133600,75500"
st "data_valid_ack"
blo "128000,75300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "data_valid_ack"
t "std_logic"
o 15
suid 34,0
i "'0'"
)
)
)
]
shape (Rectangle
uid 1607,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "127000,51000,148000,87000"
)
oxt "43000,2000,56000,22000"
ttg (MlTextGroup
uid 1608,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*97 (Text
uid 1609,0
va (VaSet
font "Arial,8,1"
)
xt "126700,87000,132900,88000"
st "FACT_FAD_lib"
blo "126700,87800"
tm "BdLibraryNameMgr"
)
*98 (Text
uid 1610,0
va (VaSet
font "Arial,8,1"
)
xt "126700,88000,132400,89000"
st "w5300_modul"
blo "126700,88800"
tm "CptNameMgr"
)
*99 (Text
uid 1611,0
va (VaSet
font "Arial,8,1"
)
xt "126700,89000,133400,90000"
st "I_main_ethernet"
blo "126700,89800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1612,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1613,0
text (MLText
uid 1614,0
va (VaSet
font "Courier New,8,0"
)
xt "127000,50200,154500,51000"
st "RAM_ADDR_WIDTH = RAMADDRWIDTH64b+2    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
)
viewicon (ZoomableIcon
uid 1615,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "127250,85250,128750,86750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*100 (Net
uid 1680,0
decl (Decl
n "crate_id"
t "std_logic_vector"
b "(1 downto 0)"
o 9
suid 30,0
)
declText (MLText
uid 1681,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,24600,-56500,25400"
st "crate_id               : std_logic_vector(1 downto 0)"
)
)
*101 (SaComponent
uid 1768,0
optionalChildren [
*102 (CptPort
uid 1760,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1761,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-7000,63625,-6250,64375"
)
tg (CPTG
uid 1762,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1763,0
va (VaSet
)
xt "-14800,63500,-8000,64500"
st "trigger_id : (47:0)"
ju 2
blo "-8000,64300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*103 (CptPort
uid 1764,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1765,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,63625,-18000,64375"
)
tg (CPTG
uid 1766,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1767,0
va (VaSet
)
xt "-17000,63500,-14200,64500"
st "trigger"
blo "-17000,64300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "trigger"
t "std_logic"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*104 (CptPort
uid 6207,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6208,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,62625,-18000,63375"
)
tg (CPTG
uid 6209,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6210,0
va (VaSet
)
xt "-17000,62500,-15700,63500"
st "clk"
blo "-17000,63300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "clk"
t "std_logic"
o 3
suid 3,0
)
)
)
]
shape (Rectangle
uid 1769,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-18000,62000,-7000,67000"
)
oxt "32000,2000,43000,12000"
ttg (MlTextGroup
uid 1770,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*105 (Text
uid 1771,0
va (VaSet
font "Arial,8,1"
)
xt "-6300,65000,300,66000"
st "FACT_FAD_LIB"
blo "-6300,65800"
tm "BdLibraryNameMgr"
)
*106 (Text
uid 1772,0
va (VaSet
font "Arial,8,1"
)
xt "-6300,66000,300,67000"
st "trigger_counter"
blo "-6300,66800"
tm "CptNameMgr"
)
*107 (Text
uid 1773,0
va (VaSet
font "Arial,8,1"
)
xt "-6300,67000,1300,68000"
st "I_main_ext_trigger"
blo "-6300,67800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1774,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1775,0
text (MLText
uid 1776,0
va (VaSet
font "Courier New,8,0"
)
xt "-18000,61000,-18000,61000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 1777,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-17750,65250,-16250,66750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*108 (Net
uid 1981,0
lang 2
decl (Decl
n "trigger_id"
t "std_logic_vector"
b "(47 downto 0)"
preAdd 0
posAdd 0
o 72
suid 34,0
)
declText (MLText
uid 1982,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,77000,-52500,77800"
st "SIGNAL trigger_id             : std_logic_vector(47 downto 0)"
)
)
*109 (Net
uid 2297,0
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 64
suid 36,0
)
declText (MLText
uid 2298,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,70600,-45000,71400"
st "SIGNAL ram_start_addr         : std_logic_vector(RAMADDRWIDTH64b-1 DOWNTO 0)"
)
)
*110 (SaComponent
uid 2311,0
optionalChildren [
*111 (CptPort
uid 2307,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2308,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,69625,72000,70375"
)
tg (CPTG
uid 2309,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2310,0
va (VaSet
font "arial,8,0"
)
xt "73000,69500,91400,70500"
st "ram_start_addr : (RAM_ADDR_WIDTH_64B-1:0)"
blo "73000,70300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH_64B-1 DOWNTO 0)"
preAdd 0
posAdd 0
o 18
suid 1,0
i "(others => '0')"
)
)
)
*112 (CptPort
uid 2351,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2352,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,67625,72000,68375"
)
tg (CPTG
uid 2353,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2354,0
va (VaSet
font "arial,8,0"
)
xt "73000,67500,74300,68500"
st "clk"
blo "73000,68300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "clk"
t "std_logic"
o 1
suid 2,0
)
)
)
*113 (CptPort
uid 2361,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2362,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,76625,72000,77375"
)
tg (CPTG
uid 2363,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2364,0
va (VaSet
font "arial,8,0"
)
xt "73000,76500,78100,77500"
st "config_ready"
blo "73000,77300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 6
suid 5,0
i "'0'"
)
)
)
*114 (CptPort
uid 2365,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2366,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,74625,72000,75375"
)
tg (CPTG
uid 2367,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2368,0
va (VaSet
font "arial,8,0"
)
xt "73000,74500,77800,75500"
st "config_start"
blo "73000,75300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "config_start"
t "std_logic"
o 2
suid 3,0
)
)
)
*115 (CptPort
uid 2369,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2370,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,70625,72000,71375"
)
tg (CPTG
uid 2371,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2372,0
va (VaSet
font "arial,8,0"
)
xt "73000,70500,78300,71500"
st "ram_write_ea"
blo "73000,71300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "ram_write_ea"
t "std_logic"
o 5
suid 4,0
i "'0'"
)
)
)
*116 (CptPort
uid 2373,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2374,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,71625,72000,72375"
)
tg (CPTG
uid 2375,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2376,0
va (VaSet
font "arial,8,0"
)
xt "73000,71500,79300,72500"
st "ram_write_ready"
blo "73000,72300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "ram_write_ready"
t "std_logic"
o 3
suid 12,0
)
)
)
*117 (CptPort
uid 2377,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2378,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,77625,72000,78375"
)
tg (CPTG
uid 2379,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2380,0
va (VaSet
font "arial,8,0"
)
xt "73000,77500,76000,78500"
st "roi_max"
blo "73000,78300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "roi_max"
t "roi_max_type"
posAdd 0
o 8
suid 14,0
i "(others => conv_std_logic_vector (0, 11))"
)
)
)
*118 (CptPort
uid 2381,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2382,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,67625,103750,68375"
)
tg (CPTG
uid 2383,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2384,0
va (VaSet
font "arial,8,0"
)
xt "98600,67500,102000,68500"
st "wiz_busy"
ju 2
blo "102000,68300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "wiz_busy"
t "std_logic"
o 16
suid 13,0
)
)
)
*119 (CptPort
uid 2385,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2386,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,71625,103750,72375"
)
tg (CPTG
uid 2387,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2388,0
va (VaSet
font "arial,8,0"
)
xt "90200,71500,102000,72500"
st "wiz_number_of_channels : (3:0)"
ju 2
blo "102000,72300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 12
suid 6,0
i "(others => '0')"
)
)
)
*120 (CptPort
uid 2389,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2390,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,70625,103750,71375"
)
tg (CPTG
uid 2391,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2392,0
va (VaSet
font "arial,8,0"
)
xt "82100,70500,102000,71500"
st "wiz_ram_start_addr : (RAM_ADDR_WIDTH_16B-1:0)"
ju 2
blo "102000,71300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAM_ADDR_WIDTH_16B-1 downto 0)"
preAdd 0
o 10
suid 7,0
i "(others => '0')"
)
)
)
*121 (CptPort
uid 2393,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2394,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,68625,103750,69375"
)
tg (CPTG
uid 2395,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2396,0
va (VaSet
font "arial,8,0"
)
xt "96900,68500,102000,69500"
st "wiz_write_ea"
ju 2
blo "102000,69300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 13
suid 8,0
i "'0'"
)
)
)
*122 (CptPort
uid 2397,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2398,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,72625,103750,73375"
)
tg (CPTG
uid 2399,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2400,0
va (VaSet
font "arial,8,0"
)
xt "96500,72500,102000,73500"
st "wiz_write_end"
ju 2
blo "102000,73300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_end"
t "std_logic"
o 15
suid 9,0
i "'0'"
)
)
)
*123 (CptPort
uid 2401,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2402,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,73625,103750,74375"
)
tg (CPTG
uid 2403,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2404,0
va (VaSet
font "arial,8,0"
)
xt "95400,73500,102000,74500"
st "wiz_write_header"
ju 2
blo "102000,74300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_header"
t "std_logic"
o 14
suid 10,0
i "'0'"
)
)
)
*124 (CptPort
uid 2405,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2406,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,69625,103750,70375"
)
tg (CPTG
uid 2407,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 2408,0
va (VaSet
font "arial,8,0"
)
xt "92600,69500,102000,70500"
st "wiz_write_length : (16:0)"
ju 2
blo "102000,70300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 11
suid 11,0
i "(others => '0')"
)
)
)
*125 (CptPort
uid 2454,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2455,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,84625,72000,85375"
)
tg (CPTG
uid 2456,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2457,0
va (VaSet
font "arial,8,0"
)
xt "73000,84500,76400,85500"
st "roi_array"
blo "73000,85300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "roi_array"
t "roi_array_type"
o 4
suid 15,0
)
)
)
*126 (CptPort
uid 2628,0
ps "OnEdgeStrategy"
shape (Triangle
uid 2629,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,78625,72000,79375"
)
tg (CPTG
uid 2630,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 2631,0
va (VaSet
font "arial,8,0"
)
xt "73000,78500,82100,79500"
st "package_length : (15:0)"
blo "73000,79300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 9
suid 18,0
i "(others => '0')"
)
)
)
*127 (CptPort
uid 5991,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5992,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "71250,75625,72000,76375"
)
tg (CPTG
uid 5993,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5994,0
va (VaSet
font "arial,8,0"
)
xt "73000,75500,78600,76500"
st "config_started"
blo "73000,76300"
)
)
thePort (LogicalPort
lang 2
m 1
decl (Decl
n "config_started"
t "std_logic"
o 7
suid 21,0
i "'0'"
)
)
)
*128 (CptPort
uid 8410,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8411,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "103000,74625,103750,75375"
)
tg (CPTG
uid 8412,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8413,0
va (VaSet
font "arial,8,0"
)
xt "99000,74500,102000,75500"
st "wiz_ack"
ju 2
blo "102000,75300"
)
)
thePort (LogicalPort
lang 2
decl (Decl
n "wiz_ack"
t "std_logic"
o 17
suid 22,0
)
)
)
]
shape (Rectangle
uid 2312,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "72000,67000,103000,87000"
)
oxt "15000,6000,23000,16000"
ttg (MlTextGroup
uid 2313,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*129 (Text
uid 2314,0
va (VaSet
font "arial,8,1"
)
xt "72350,87000,78550,88000"
st "FACT_FAD_lib"
blo "72350,87800"
tm "BdLibraryNameMgr"
)
*130 (Text
uid 2315,0
va (VaSet
font "arial,8,1"
)
xt "72350,88000,79650,89000"
st "memory_manager"
blo "72350,88800"
tm "CptNameMgr"
)
*131 (Text
uid 2316,0
va (VaSet
font "arial,8,1"
)
xt "72350,89000,82850,90000"
st "I_main_memory_manager"
blo "72350,89800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 2317,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 2318,0
text (MLText
uid 2319,0
va (VaSet
font "Courier New,8,0"
)
xt "72000,65400,101500,67000"
st "RAM_ADDR_WIDTH_64B = RAMADDRWIDTH64b      ( integer )  
RAM_ADDR_WIDTH_16B = RAMADDRWIDTH64b+2    ( integer )  "
)
header ""
)
elements [
(GiElement
name "RAM_ADDR_WIDTH_64B"
type "integer"
value "RAMADDRWIDTH64b"
)
(GiElement
name "RAM_ADDR_WIDTH_16B"
type "integer"
value "RAMADDRWIDTH64b+2"
)
]
)
viewicon (ZoomableIcon
uid 2320,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "72250,85250,73750,86750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*132 (Net
uid 2468,0
lang 2
decl (Decl
n "wiz_busy"
t "std_logic"
o 73
suid 38,0
)
declText (MLText
uid 2469,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,78600,-62500,79400"
st "SIGNAL wiz_busy               : std_logic"
)
)
*133 (Net
uid 2474,0
lang 2
decl (Decl
n "wiz_write_ea"
t "std_logic"
o 76
suid 39,0
i "'0'"
)
declText (MLText
uid 2475,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,81000,-41500,81800"
st "SIGNAL wiz_write_ea           : std_logic                                    := '0'"
)
)
*134 (Net
uid 2480,0
lang 2
decl (Decl
n "wiz_write_length"
t "std_logic_vector"
b "(16 downto 0)"
o 79
suid 40,0
i "(others => '0')"
)
declText (MLText
uid 2481,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,83400,-35500,84200"
st "SIGNAL wiz_write_length       : std_logic_vector(16 downto 0)                := (others => '0')"
)
)
*135 (Net
uid 2486,0
lang 2
decl (Decl
n "wiz_ram_start_addr"
t "std_logic_vector"
b "(RAMADDRWIDTH64b+1 DOWNTO 0)"
preAdd 0
o 75
suid 41,0
i "(others => '0')"
)
declText (MLText
uid 2487,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,80200,-35500,81000"
st "SIGNAL wiz_ram_start_addr     : std_logic_vector(RAMADDRWIDTH64b+1 DOWNTO 0) := (others => '0')"
)
)
*136 (Net
uid 2492,0
lang 2
decl (Decl
n "wiz_number_of_channels"
t "std_logic_vector"
b "(3 downto 0)"
o 74
suid 42,0
i "(others => '0')"
)
declText (MLText
uid 2493,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,79400,-35500,80200"
st "SIGNAL wiz_number_of_channels : std_logic_vector(3 downto 0)                 := (others => '0')"
)
)
*137 (Net
uid 2498,0
lang 2
decl (Decl
n "wiz_write_end"
t "std_logic"
o 77
suid 43,0
i "'0'"
)
declText (MLText
uid 2499,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,81800,-41500,82600"
st "SIGNAL wiz_write_end          : std_logic                                    := '0'"
)
)
*138 (Net
uid 2504,0
lang 2
decl (Decl
n "wiz_write_header"
t "std_logic"
o 78
suid 44,0
i "'0'"
)
declText (MLText
uid 2505,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,82600,-41500,83400"
st "SIGNAL wiz_write_header       : std_logic                                    := '0'"
)
)
*139 (Net
uid 2574,0
decl (Decl
n "ram_write_ea"
t "std_logic"
o 65
suid 48,0
)
declText (MLText
uid 2575,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,71400,-62500,72200"
st "SIGNAL ram_write_ea           : std_logic"
)
)
*140 (Net
uid 2580,0
decl (Decl
n "ram_write_ready"
t "std_logic"
o 66
suid 49,0
i "'0'"
)
declText (MLText
uid 2581,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,72200,-41500,73000"
st "SIGNAL ram_write_ready        : std_logic                                    := '0'"
)
)
*141 (Net
uid 2586,0
decl (Decl
n "config_start"
t "std_logic"
o 44
suid 50,0
i "'0'"
)
declText (MLText
uid 2587,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,54600,-41500,55400"
st "SIGNAL config_start           : std_logic                                    := '0'"
)
)
*142 (Net
uid 2592,0
decl (Decl
n "config_ready"
t "std_logic"
o 41
suid 51,0
)
declText (MLText
uid 2593,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,52200,-62500,53000"
st "SIGNAL config_ready           : std_logic"
)
)
*143 (Net
uid 2598,0
decl (Decl
n "roi_max"
t "roi_max_type"
o 68
suid 52,0
)
declText (MLText
uid 2599,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,73800,-61000,74600"
st "SIGNAL roi_max                : roi_max_type"
)
)
*144 (Net
uid 2640,0
decl (Decl
n "package_length"
t "std_logic_vector"
b "(15 downto 0)"
o 61
suid 54,0
)
declText (MLText
uid 2641,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,68200,-52500,69000"
st "SIGNAL package_length         : std_logic_vector(15 downto 0)"
)
)
*145 (Net
uid 2776,0
decl (Decl
n "adc_oeb"
t "std_logic"
o 16
suid 57,0
i "'1'"
)
declText (MLText
uid 2777,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,30200,-45000,31000"
st "adc_oeb                : std_logic                                    := '1'"
)
)
*146 (PortIoOut
uid 2798,0
shape (CompositeShape
uid 2799,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2800,0
sl 0
ro 90
xt "-28000,81625,-26500,82375"
)
(Line
uid 2801,0
sl 0
ro 90
xt "-26500,82000,-26000,82000"
pts [
"-26000,82000"
"-26500,82000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2802,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2803,0
va (VaSet
)
xt "-32200,81500,-29000,82500"
st "adc_oeb"
ju 2
blo "-29000,82300"
tm "WireNameMgr"
)
)
)
*147 (PortIoIn
uid 2804,0
shape (CompositeShape
uid 2805,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2806,0
sl 0
ro 270
xt "-28000,76625,-26500,77375"
)
(Line
uid 2807,0
sl 0
ro 270
xt "-26500,77000,-26000,77000"
pts [
"-26500,77000"
"-26000,77000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2808,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2809,0
va (VaSet
)
xt "-34400,76500,-29000,77500"
st "adc_otr_array"
ju 2
blo "-29000,77300"
tm "WireNameMgr"
)
)
)
*148 (Net
uid 2924,0
decl (Decl
n "roi_array"
t "roi_array_type"
o 67
suid 65,0
)
declText (MLText
uid 2925,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,73000,-60000,73800"
st "SIGNAL roi_array              : roi_array_type"
)
)
*149 (PortIoIn
uid 2950,0
shape (CompositeShape
uid 2951,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2952,0
sl 0
ro 270
xt "-28000,85625,-26500,86375"
)
(Line
uid 2953,0
sl 0
ro 270
xt "-26500,86000,-26000,86000"
pts [
"-26500,86000"
"-26000,86000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2954,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2955,0
va (VaSet
)
xt "-32300,85500,-29000,86500"
st "board_id"
ju 2
blo "-29000,86300"
tm "WireNameMgr"
)
)
)
*150 (PortIoIn
uid 2956,0
shape (CompositeShape
uid 2957,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 2958,0
sl 0
ro 270
xt "-28000,86625,-26500,87375"
)
(Line
uid 2959,0
sl 0
ro 270
xt "-26500,87000,-26000,87000"
pts [
"-26500,87000"
"-26000,87000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 2960,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2961,0
va (VaSet
)
xt "-32100,86500,-29000,87500"
st "crate_id"
ju 2
blo "-29000,87300"
tm "WireNameMgr"
)
)
)
*151 (Grouping
uid 3137,0
optionalChildren [
*152 (CommentText
uid 3139,0
shape (Rectangle
uid 3140,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "125000,175000,142000,176000"
)
oxt "18000,70000,35000,71000"
text (MLText
uid 3141,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "125200,175000,134500,176000"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*153 (CommentText
uid 3142,0
shape (Rectangle
uid 3143,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "142000,171000,146000,172000"
)
oxt "35000,66000,39000,67000"
text (MLText
uid 3144,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "142200,171000,145200,172000"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*154 (CommentText
uid 3145,0
shape (Rectangle
uid 3146,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "125000,173000,142000,174000"
)
oxt "18000,68000,35000,69000"
text (MLText
uid 3147,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "125200,173000,135200,174000"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
*155 (CommentText
uid 3148,0
shape (Rectangle
uid 3149,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,173000,125000,174000"
)
oxt "14000,68000,18000,69000"
text (MLText
uid 3150,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "121200,173000,123300,174000"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*156 (CommentText
uid 3151,0
shape (Rectangle
uid 3152,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "142000,172000,162000,176000"
)
oxt "35000,67000,55000,71000"
text (MLText
uid 3153,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "142200,172200,151400,173200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 4000
visibleWidth 20000
)
ignorePrefs 1
titleBlock 1
)
*157 (CommentText
uid 3154,0
shape (Rectangle
uid 3155,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "146000,171000,162000,172000"
)
oxt "39000,66000,55000,67000"
text (MLText
uid 3156,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "146200,171000,150700,172000"
st "
%project_name
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 16000
)
position 1
ignorePrefs 1
titleBlock 1
)
*158 (CommentText
uid 3157,0
shape (Rectangle
uid 3158,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,171000,142000,173000"
)
oxt "14000,66000,35000,68000"
text (MLText
uid 3159,0
va (VaSet
fg "32768,0,0"
)
xt "128700,171000,134300,173000"
st "
TU Dortmund 
Physik / EE
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 2000
visibleWidth 21000
)
position 1
ignorePrefs 1
titleBlock 1
)
*159 (CommentText
uid 3160,0
shape (Rectangle
uid 3161,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,174000,125000,175000"
)
oxt "14000,69000,18000,70000"
text (MLText
uid 3162,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "121200,174000,123300,175000"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*160 (CommentText
uid 3163,0
shape (Rectangle
uid 3164,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,175000,125000,176000"
)
oxt "14000,70000,18000,71000"
text (MLText
uid 3165,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "121200,175000,123900,176000"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 4000
)
position 1
ignorePrefs 1
titleBlock 1
)
*161 (CommentText
uid 3166,0
shape (Rectangle
uid 3167,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "125000,174000,142000,175000"
)
oxt "18000,69000,35000,70000"
text (MLText
uid 3168,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "125200,174000,137600,175000"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1000
visibleWidth 17000
)
position 1
ignorePrefs 1
titleBlock 1
)
]
shape (GroupingShape
uid 3138,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "121000,171000,162000,176000"
)
oxt "14000,66000,55000,71000"
)
*162 (Net
uid 3894,0
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 12
suid 81,0
)
declText (MLText
uid 3895,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,27000,-66500,27800"
st "CLK_25_PS              : std_logic"
)
)
*163 (PortIoOut
uid 3978,0
shape (CompositeShape
uid 3979,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 3980,0
sl 0
ro 90
xt "-28000,30625,-26500,31375"
)
(Line
uid 3981,0
sl 0
ro 90
xt "-26500,31000,-26000,31000"
pts [
"-26000,31000"
"-26500,31000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 3982,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3983,0
va (VaSet
)
xt "-33500,30500,-29000,31500"
st "CLK_25_PS"
ju 2
blo "-29000,31300"
tm "WireNameMgr"
)
)
)
*164 (Net
uid 4068,0
decl (Decl
n "CLK_50"
t "std_logic"
o 13
suid 90,0
)
declText (MLText
uid 4069,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,27800,-66500,28600"
st "CLK_50                 : std_logic"
)
)
*165 (SaComponent
uid 4194,0
optionalChildren [
*166 (CptPort
uid 4178,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4179,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,18625,-1250,19375"
)
tg (CPTG
uid 4180,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4181,0
va (VaSet
font "arial,8,0"
)
xt "-6100,18500,-3000,19500"
st "CLK_50"
ju 2
blo "-3000,19300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_50"
t "std_logic"
o 4
suid 2,0
)
)
)
*167 (CptPort
uid 4182,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4183,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,20625,-1250,21375"
)
tg (CPTG
uid 4184,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4185,0
va (VaSet
font "arial,8,0"
)
xt "-6100,20500,-3000,21500"
st "CLK_25"
ju 2
blo "-3000,21300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25"
t "std_logic"
o 2
suid 3,0
)
)
)
*168 (CptPort
uid 4186,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4187,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-2000,22625,-1250,23375"
)
tg (CPTG
uid 4188,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4189,0
va (VaSet
font "arial,8,0"
)
xt "-7500,22500,-3000,23500"
st "CLK_25_PS"
ju 2
blo "-3000,23300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "CLK_25_PS"
t "std_logic"
o 3
suid 4,0
)
)
)
*169 (CptPort
uid 4190,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4191,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-20750,18625,-20000,19375"
)
tg (CPTG
uid 4192,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4193,0
va (VaSet
font "arial,8,0"
)
xt "-19000,18500,-17100,19500"
st "CLK"
blo "-19000,19300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 6,0
)
)
)
]
shape (Rectangle
uid 4195,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-20000,18000,-2000,25000"
)
oxt "28000,13000,46000,20000"
ttg (MlTextGroup
uid 4196,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*170 (Text
uid 4197,0
va (VaSet
font "arial,8,1"
)
xt "-13800,26000,-7600,27000"
st "FACT_FAD_lib"
blo "-13800,26800"
tm "BdLibraryNameMgr"
)
*171 (Text
uid 4198,0
va (VaSet
font "arial,8,1"
)
xt "-13800,27000,-7100,28000"
st "clock_generator"
blo "-13800,27800"
tm "CptNameMgr"
)
*172 (Text
uid 4199,0
va (VaSet
font "arial,8,1"
)
xt "-13800,28000,-6500,29000"
st "I_main_clock_gen"
blo "-13800,28800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4200,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4201,0
text (MLText
uid 4202,0
va (VaSet
font "Courier New,8,0"
)
xt "-35000,24000,-35000,24000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 4203,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-19750,23250,-18250,24750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*173 (Net
uid 4204,0
decl (Decl
n "CLK_25"
t "std_logic"
o 32
suid 91,0
)
declText (MLText
uid 4205,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,45000,-62500,45800"
st "SIGNAL CLK_25                 : std_logic"
)
)
*174 (PortIoOut
uid 4220,0
shape (CompositeShape
uid 4221,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4222,0
sl 0
ro 90
xt "-28000,33625,-26500,34375"
)
(Line
uid 4223,0
sl 0
ro 90
xt "-26500,34000,-26000,34000"
pts [
"-26000,34000"
"-26500,34000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4224,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4225,0
va (VaSet
)
xt "-32100,33500,-29000,34500"
st "CLK_50"
ju 2
blo "-29000,34300"
tm "WireNameMgr"
)
)
)
*175 (Net
uid 4232,0
decl (Decl
n "CLK"
t "std_logic"
o 1
suid 92,0
)
declText (MLText
uid 4233,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,18200,-66500,19000"
st "CLK                    : std_logic"
)
)
*176 (Net
uid 4260,0
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 7
suid 95,0
)
declText (MLText
uid 4261,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,23000,-56500,23800"
st "adc_otr_array          : std_logic_vector(3 DOWNTO 0)"
)
)
*177 (Net
uid 4270,0
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 6
suid 96,0
)
declText (MLText
uid 4271,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,22200,-61000,23000"
st "adc_data_array         : adc_data_array_type"
)
)
*178 (PortIoIn
uid 4307,0
shape (CompositeShape
uid 4308,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4309,0
sl 0
ro 270
xt "-28000,75625,-26500,76375"
)
(Line
uid 4310,0
sl 0
ro 270
xt "-26500,76000,-26000,76000"
pts [
"-26500,76000"
"-26000,76000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4311,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4312,0
va (VaSet
)
xt "-34900,75500,-29000,76500"
st "adc_data_array"
ju 2
blo "-29000,76300"
tm "WireNameMgr"
)
)
)
*179 (Net
uid 4399,0
decl (Decl
n "drs_clk_en"
t "std_logic"
o 54
suid 97,0
i "'0'"
)
declText (MLText
uid 4400,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,62600,-41500,63400"
st "SIGNAL drs_clk_en             : std_logic                                    := '0'"
)
)
*180 (Net
uid 4405,0
decl (Decl
n "drs_s_cell_array"
t "drs_s_cell_array_type"
o 57
suid 98,0
)
declText (MLText
uid 4406,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,65000,-56500,65800"
st "SIGNAL drs_s_cell_array       : drs_s_cell_array_type"
)
)
*181 (Net
uid 4417,0
decl (Decl
n "drs_read_s_cell"
t "std_logic"
o 55
suid 100,0
i "'0'"
)
declText (MLText
uid 4418,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,63400,-41500,64200"
st "SIGNAL drs_read_s_cell        : std_logic                                    := '0'"
)
)
*182 (Net
uid 4535,0
decl (Decl
n "drs_channel_id"
t "std_logic_vector"
b "(3 downto 0)"
o 19
suid 109,0
i "(others => '0')"
)
declText (MLText
uid 4536,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,32600,-39000,33400"
st "drs_channel_id         : std_logic_vector(3 downto 0)                 := (others => '0')"
)
)
*183 (Net
uid 4543,0
decl (Decl
n "drs_dwrite"
t "std_logic"
o 20
suid 110,0
i "'1'"
)
declText (MLText
uid 4544,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,33400,-45000,34200"
st "drs_dwrite             : std_logic                                    := '1'"
)
)
*184 (PortIoOut
uid 4551,0
shape (CompositeShape
uid 4552,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4553,0
sl 0
ro 90
xt "-28000,56625,-26500,57375"
)
(Line
uid 4554,0
sl 0
ro 90
xt "-26500,57000,-26000,57000"
pts [
"-26000,57000"
"-26500,57000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4555,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4556,0
va (VaSet
)
xt "-34900,56500,-29000,57500"
st "drs_channel_id"
ju 2
blo "-29000,57300"
tm "WireNameMgr"
)
)
)
*185 (PortIoOut
uid 4557,0
shape (CompositeShape
uid 4558,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4559,0
sl 0
ro 90
xt "-28000,59625,-26500,60375"
)
(Line
uid 4560,0
sl 0
ro 90
xt "-26500,60000,-26000,60000"
pts [
"-26000,60000"
"-26500,60000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4561,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4562,0
va (VaSet
)
xt "-33300,59500,-29000,60500"
st "drs_dwrite"
ju 2
blo "-29000,60300"
tm "WireNameMgr"
)
)
)
*186 (Net
uid 4669,0
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 2
suid 112,0
)
declText (MLText
uid 4670,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,19000,-66500,19800"
st "SROUT_in_0             : std_logic"
)
)
*187 (Net
uid 4677,0
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 3
suid 113,0
)
declText (MLText
uid 4678,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,19800,-66500,20600"
st "SROUT_in_1             : std_logic"
)
)
*188 (Net
uid 4685,0
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 4
suid 114,0
)
declText (MLText
uid 4686,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,20600,-66500,21400"
st "SROUT_in_2             : std_logic"
)
)
*189 (Net
uid 4693,0
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 5
suid 115,0
)
declText (MLText
uid 4694,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,21400,-66500,22200"
st "SROUT_in_3             : std_logic"
)
)
*190 (PortIoIn
uid 4701,0
shape (CompositeShape
uid 4702,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4703,0
sl 0
ro 270
xt "-28000,46625,-26500,47375"
)
(Line
uid 4704,0
sl 0
ro 270
xt "-26500,47000,-26000,47000"
pts [
"-26500,47000"
"-26000,47000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4705,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4706,0
va (VaSet
)
xt "-34400,46500,-29000,47500"
st "SROUT_in_0"
ju 2
blo "-29000,47300"
tm "WireNameMgr"
)
)
)
*191 (PortIoIn
uid 4707,0
shape (CompositeShape
uid 4708,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4709,0
sl 0
ro 270
xt "-28000,47625,-26500,48375"
)
(Line
uid 4710,0
sl 0
ro 270
xt "-26500,48000,-26000,48000"
pts [
"-26500,48000"
"-26000,48000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4711,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4712,0
va (VaSet
)
xt "-34400,47500,-29000,48500"
st "SROUT_in_1"
ju 2
blo "-29000,48300"
tm "WireNameMgr"
)
)
)
*192 (PortIoIn
uid 4713,0
shape (CompositeShape
uid 4714,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4715,0
sl 0
ro 270
xt "-28000,48625,-26500,49375"
)
(Line
uid 4716,0
sl 0
ro 270
xt "-26500,49000,-26000,49000"
pts [
"-26500,49000"
"-26000,49000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4717,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4718,0
va (VaSet
)
xt "-34400,48500,-29000,49500"
st "SROUT_in_2"
ju 2
blo "-29000,49300"
tm "WireNameMgr"
)
)
)
*193 (PortIoIn
uid 4719,0
shape (CompositeShape
uid 4720,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4721,0
sl 0
ro 270
xt "-28000,49625,-26500,50375"
)
(Line
uid 4722,0
sl 0
ro 270
xt "-26500,50000,-26000,50000"
pts [
"-26500,50000"
"-26000,50000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4723,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4724,0
va (VaSet
)
xt "-34400,49500,-29000,50500"
st "SROUT_in_3"
ju 2
blo "-29000,50300"
tm "WireNameMgr"
)
)
)
*194 (Net
uid 4741,0
decl (Decl
n "drs_read_s_cell_ready"
t "std_logic"
o 56
suid 116,0
)
declText (MLText
uid 4742,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,64200,-62500,65000"
st "SIGNAL drs_read_s_cell_ready  : std_logic"
)
)
*195 (SaComponent
uid 4903,0
optionalChildren [
*196 (CptPort
uid 4867,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4868,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,44625,-18000,45375"
)
tg (CPTG
uid 4869,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4870,0
va (VaSet
)
xt "-17000,44500,-15100,45500"
st "CLK"
blo "-17000,45300"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_logic"
o 1
)
)
)
*197 (CptPort
uid 4871,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4872,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "1000,52625,1750,53375"
)
tg (CPTG
uid 4873,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4874,0
va (VaSet
)
xt "-7500,52500,0,53500"
st "start_endless_mode"
ju 2
blo "0,53300"
)
)
thePort (LogicalPort
decl (Decl
n "start_endless_mode"
t "std_logic"
o 2
)
)
)
*198 (CptPort
uid 4875,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4876,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "1000,49625,1750,50375"
)
tg (CPTG
uid 4877,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4878,0
va (VaSet
)
xt "-10200,49500,0,50500"
st "start_read_stop_pos_mode"
ju 2
blo "0,50300"
)
)
thePort (LogicalPort
decl (Decl
n "start_read_stop_pos_mode"
t "std_logic"
o 3
)
)
)
*199 (CptPort
uid 4879,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4880,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,46625,-18000,47375"
)
tg (CPTG
uid 4881,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4882,0
va (VaSet
)
xt "-17000,46500,-11600,47500"
st "SROUT_in_0"
blo "-17000,47300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_0"
t "std_logic"
o 4
)
)
)
*200 (CptPort
uid 4883,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4884,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,47625,-18000,48375"
)
tg (CPTG
uid 4885,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4886,0
va (VaSet
)
xt "-17000,47500,-11600,48500"
st "SROUT_in_1"
blo "-17000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_1"
t "std_logic"
o 5
)
)
)
*201 (CptPort
uid 4887,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4888,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,48625,-18000,49375"
)
tg (CPTG
uid 4889,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4890,0
va (VaSet
)
xt "-17000,48500,-11600,49500"
st "SROUT_in_2"
blo "-17000,49300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_2"
t "std_logic"
o 6
)
)
)
*202 (CptPort
uid 4891,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4892,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,49625,-18000,50375"
)
tg (CPTG
uid 4893,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4894,0
va (VaSet
)
xt "-17000,49500,-11600,50500"
st "SROUT_in_3"
blo "-17000,50300"
)
)
thePort (LogicalPort
decl (Decl
n "SROUT_in_3"
t "std_logic"
o 7
)
)
)
*203 (CptPort
uid 4895,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4896,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "1000,51625,1750,52375"
)
tg (CPTG
uid 4897,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4898,0
va (VaSet
)
xt "-3400,51500,0,52500"
st "stop_pos"
ju 2
blo "0,52300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "stop_pos"
t "drs_s_cell_array_type"
o 8
)
)
)
*204 (CptPort
uid 4899,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4900,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "1000,50625,1750,51375"
)
tg (CPTG
uid 4901,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 4902,0
va (VaSet
)
xt "-5700,50500,0,51500"
st "stop_pos_valid"
ju 2
blo "0,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "stop_pos_valid"
t "std_logic"
o 9
i "'0'"
)
)
)
*205 (CptPort
uid 4938,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4939,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,50625,-18000,51375"
)
tg (CPTG
uid 4940,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4941,0
va (VaSet
)
xt "-17000,50500,-12800,51500"
st "RSRLOAD"
blo "-17000,51300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "RSRLOAD"
t "std_logic"
o 10
i "'0'"
)
)
)
*206 (CptPort
uid 4942,0
ps "OnEdgeStrategy"
shape (Triangle
uid 4943,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,51625,-18000,52375"
)
tg (CPTG
uid 4944,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 4945,0
va (VaSet
)
xt "-17000,51500,-14000,52500"
st "SRCLK"
blo "-17000,52300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "SRCLK"
t "std_logic"
o 11
i "'0'"
)
)
)
]
shape (Rectangle
uid 4904,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-18000,44000,1000,54000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 4905,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*207 (Text
uid 4906,0
va (VaSet
font "Arial,8,1"
)
xt "-17400,54000,-10800,55000"
st "FACT_FAD_LIB"
blo "-17400,54800"
tm "BdLibraryNameMgr"
)
*208 (Text
uid 4907,0
va (VaSet
font "Arial,8,1"
)
xt "-17400,55000,-12700,56000"
st "drs_pulser"
blo "-17400,55800"
tm "CptNameMgr"
)
*209 (Text
uid 4908,0
va (VaSet
font "Arial,8,1"
)
xt "-17400,56000,-9900,57000"
st "I_main_drs_pulser"
blo "-17400,56800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 4909,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 4910,0
text (MLText
uid 4911,0
va (VaSet
font "Courier New,8,0"
)
xt "-8500,46000,-8500,46000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 4912,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-17750,52250,-16250,53750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*210 (Net
uid 4946,0
decl (Decl
n "RSRLOAD"
t "std_logic"
o 14
suid 117,0
i "'0'"
)
declText (MLText
uid 4947,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,28600,-45000,29400"
st "RSRLOAD                : std_logic                                    := '0'"
)
)
*211 (PortIoOut
uid 4954,0
shape (CompositeShape
uid 4955,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4956,0
sl 0
ro 90
xt "-28000,50625,-26500,51375"
)
(Line
uid 4957,0
sl 0
ro 90
xt "-26500,51000,-26000,51000"
pts [
"-26000,51000"
"-26500,51000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4958,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4959,0
va (VaSet
)
xt "-33200,50500,-29000,51500"
st "RSRLOAD"
ju 2
blo "-29000,51300"
tm "WireNameMgr"
)
)
)
*212 (Net
uid 4960,0
decl (Decl
n "SRCLK"
t "std_logic"
o 15
suid 118,0
i "'0'"
)
declText (MLText
uid 4961,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,29400,-45000,30200"
st "SRCLK                  : std_logic                                    := '0'"
)
)
*213 (PortIoOut
uid 4968,0
shape (CompositeShape
uid 4969,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 4970,0
sl 0
ro 90
xt "-28000,51625,-26500,52375"
)
(Line
uid 4971,0
sl 0
ro 90
xt "-26500,52000,-26000,52000"
pts [
"-26000,52000"
"-26500,52000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 4972,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4973,0
va (VaSet
)
xt "-32000,51500,-29000,52500"
st "SRCLK"
ju 2
blo "-29000,52300"
tm "WireNameMgr"
)
)
)
*214 (SaComponent
uid 5072,0
optionalChildren [
*215 (CptPort
uid 5028,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5029,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,99625,74000,100375"
)
tg (CPTG
uid 5030,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5031,0
va (VaSet
)
xt "75000,99500,76300,100500"
st "clk"
blo "75000,100300"
)
)
thePort (LogicalPort
decl (Decl
n "clk"
t "STD_LOGIC"
o 1
suid 1,0
)
)
)
*216 (CptPort
uid 5032,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5033,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,99625,92750,100375"
)
tg (CPTG
uid 5034,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5035,0
va (VaSet
)
xt "84000,99500,91000,100500"
st "config_addr : (7:0)"
ju 2
blo "91000,100300"
)
)
thePort (LogicalPort
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 2
suid 2,0
)
)
)
*217 (CptPort
uid 5036,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5037,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,101625,92750,102375"
)
tg (CPTG
uid 5038,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5039,0
va (VaSet
)
xt "84400,101500,91000,102500"
st "config_data_valid"
ju 2
blo "91000,102300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_data_valid"
t "std_logic"
o 7
suid 3,0
)
)
)
*218 (CptPort
uid 5040,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5041,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,105625,92750,106375"
)
tg (CPTG
uid 5042,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5043,0
va (VaSet
)
xt "86200,105500,91000,106500"
st "config_busy"
ju 2
blo "91000,106300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_busy"
t "std_logic"
o 6
suid 4,0
)
)
)
*219 (CptPort
uid 5044,0
ps "OnEdgeStrategy"
shape (Diamond
uid 5045,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,100625,92750,101375"
)
tg (CPTG
uid 5046,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5047,0
va (VaSet
)
xt "83300,100500,91000,101500"
st "config_data : (15:0)"
ju 2
blo "91000,101300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "config_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 12
suid 5,0
)
)
)
*220 (CptPort
uid 5048,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5049,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,101625,74000,102375"
)
tg (CPTG
uid 5050,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5051,0
va (VaSet
)
xt "75000,101500,78400,102500"
st "roi_array"
blo "75000,102300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "roi_array"
t "roi_array_type"
o 11
suid 6,0
)
)
)
*221 (CptPort
uid 5052,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5053,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,103625,92750,104375"
)
tg (CPTG
uid 5054,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5055,0
va (VaSet
)
xt "85700,103500,91000,104500"
st "config_wr_en"
ju 2
blo "91000,104300"
)
)
thePort (LogicalPort
decl (Decl
n "config_wr_en"
t "std_logic"
o 5
suid 7,0
)
)
)
*222 (CptPort
uid 5056,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5057,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,108625,74000,109375"
)
tg (CPTG
uid 5058,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5059,0
va (VaSet
)
xt "75000,108500,78700,109500"
st "dac_array"
blo "75000,109300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_array"
t "dac_array_type"
o 10
suid 8,0
)
)
)
*223 (CptPort
uid 5060,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5061,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "92000,104625,92750,105375"
)
tg (CPTG
uid 5062,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5063,0
va (VaSet
)
xt "85800,104500,91000,105500"
st "config_rd_en"
ju 2
blo "91000,105300"
)
)
thePort (LogicalPort
decl (Decl
n "config_rd_en"
t "std_logic"
o 3
suid 9,0
)
)
)
*224 (CptPort
uid 5064,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5065,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,102625,74000,103375"
)
tg (CPTG
uid 5066,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5067,0
va (VaSet
)
xt "75000,102500,79800,103500"
st "config_start"
blo "75000,103300"
)
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 4
suid 10,0
)
)
)
*225 (CptPort
uid 5068,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5069,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,104625,74000,105375"
)
tg (CPTG
uid 5070,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5071,0
va (VaSet
)
xt "75000,104500,80100,105500"
st "config_ready"
blo "75000,105300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 8
suid 11,0
)
)
)
*226 (CptPort
uid 5995,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5996,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "73250,103625,74000,104375"
)
tg (CPTG
uid 5997,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5998,0
va (VaSet
)
xt "75000,103500,80600,104500"
st "config_started"
blo "75000,104300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 9
suid 12,0
i "'0'"
)
)
)
]
shape (Rectangle
uid 5073,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "74000,99000,92000,112000"
)
oxt "15000,13000,33000,26000"
ttg (MlTextGroup
uid 5074,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*227 (Text
uid 5075,0
va (VaSet
font "Arial,8,1"
)
xt "74200,112000,80400,113000"
st "FACT_FAD_lib"
blo "74200,112800"
tm "BdLibraryNameMgr"
)
*228 (Text
uid 5076,0
va (VaSet
font "Arial,8,1"
)
xt "74200,113000,79600,114000"
st "control_unit"
blo "74200,113800"
tm "CptNameMgr"
)
*229 (Text
uid 5077,0
va (VaSet
font "Arial,8,1"
)
xt "74200,114000,82400,115000"
st "I_main_control_unit"
blo "74200,114800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5078,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5079,0
text (MLText
uid 5080,0
va (VaSet
font "Courier New,8,0"
)
xt "59000,98800,59000,98800"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 5081,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "74250,110250,75750,111750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*230 (Net
uid 5088,0
decl (Decl
n "config_addr"
t "std_logic_vector"
b "(7 DOWNTO 0)"
o 36
suid 119,0
)
declText (MLText
uid 5089,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,48200,-53000,49000"
st "SIGNAL config_addr            : std_logic_vector(7 DOWNTO 0)"
)
)
*231 (Net
uid 5096,0
decl (Decl
n "config_data_valid"
t "std_logic"
o 39
suid 120,0
)
declText (MLText
uid 5097,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,50600,-62500,51400"
st "SIGNAL config_data_valid      : std_logic"
)
)
*232 (Net
uid 5104,0
decl (Decl
n "config_busy"
t "std_logic"
o 37
suid 121,0
)
declText (MLText
uid 5105,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,49000,-62500,49800"
st "SIGNAL config_busy            : std_logic"
)
)
*233 (Net
uid 5112,0
decl (Decl
n "config_data"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 38
suid 122,0
)
declText (MLText
uid 5113,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,49800,-52500,50600"
st "SIGNAL config_data            : std_logic_vector(15 DOWNTO 0)"
)
)
*234 (Net
uid 5120,0
decl (Decl
n "config_wr_en"
t "std_logic"
o 51
suid 123,0
)
declText (MLText
uid 5121,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,60200,-62500,61000"
st "SIGNAL config_wr_en           : std_logic"
)
)
*235 (Net
uid 5128,0
decl (Decl
n "config_rd_en"
t "std_logic"
o 40
suid 124,0
)
declText (MLText
uid 5129,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,51400,-62500,52200"
st "SIGNAL config_rd_en           : std_logic"
)
)
*236 (Net
uid 5144,0
decl (Decl
n "dac_array"
t "dac_array_type"
o 52
suid 126,0
)
declText (MLText
uid 5145,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,61000,-60000,61800"
st "SIGNAL dac_array              : dac_array_type"
)
)
*237 (Net
uid 5194,0
decl (Decl
n "config_start_cm"
t "std_logic"
o 45
suid 131,0
)
declText (MLText
uid 5195,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,55400,-62500,56200"
st "SIGNAL config_start_cm        : std_logic"
)
)
*238 (Net
uid 5196,0
decl (Decl
n "config_ready_cm"
t "std_logic"
o 42
suid 132,0
)
declText (MLText
uid 5197,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,53000,-62500,53800"
st "SIGNAL config_ready_cm        : std_logic"
)
)
*239 (Net
uid 5220,0
decl (Decl
n "led"
t "std_logic_vector"
b "(7 DOWNTO 0)"
posAdd 0
o 21
suid 133,0
i "(OTHERS => '0')"
)
declText (MLText
uid 5221,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,34200,-39000,35000"
st "led                    : std_logic_vector(7 DOWNTO 0)                 := (OTHERS => '0')"
)
)
*240 (Net
uid 5279,0
decl (Decl
n "s_trigger"
t "std_logic"
o 69
suid 134,0
i "'0'"
)
declText (MLText
uid 5280,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,74600,-41500,75400"
st "SIGNAL s_trigger              : std_logic                                    := '0'"
)
)
*241 (Net
uid 5472,0
decl (Decl
n "sensor_ready"
t "std_logic"
o 71
suid 140,0
)
declText (MLText
uid 5473,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,76200,-62500,77000"
st "SIGNAL sensor_ready           : std_logic"
)
)
*242 (Net
uid 5478,0
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 70
suid 141,0
)
declText (MLText
uid 5479,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,75400,-58500,76200"
st "SIGNAL sensor_array           : sensor_array_type"
)
)
*243 (Net
uid 5588,0
decl (Decl
n "config_ready_spi"
t "std_logic"
o 43
suid 144,0
)
declText (MLText
uid 5589,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,53800,-62500,54600"
st "SIGNAL config_ready_spi       : std_logic"
)
)
*244 (Net
uid 5632,0
lang 10
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 34
suid 146,0
)
declText (MLText
uid 5633,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,46600,-53000,47400"
st "SIGNAL adc_otr                : std_logic_vector(3 DOWNTO 0)"
)
)
*245 (Net
uid 5640,0
decl (Decl
n "adc_data_array_int"
t "adc_data_array_type"
o 33
suid 147,0
)
declText (MLText
uid 5641,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,45800,-57500,46600"
st "SIGNAL adc_data_array_int     : adc_data_array_type"
)
)
*246 (SaComponent
uid 5678,0
optionalChildren [
*247 (CptPort
uid 5658,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5659,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,75625,-18000,76375"
)
tg (CPTG
uid 5660,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5661,0
va (VaSet
font "arial,8,0"
)
xt "-17000,75500,-11100,76500"
st "adc_data_array"
blo "-17000,76300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_data_array"
t "adc_data_array_type"
o 2
suid 5,0
)
)
)
*248 (CptPort
uid 5662,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5663,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,75625,750,76375"
)
tg (CPTG
uid 5664,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5665,0
va (VaSet
font "arial,8,0"
)
xt "-8100,75500,-1000,76500"
st "adc_data_array_int"
ju 2
blo "-1000,76300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "adc_data_array_int"
t "adc_data_array_type"
o 4
suid 6,0
)
)
)
*249 (CptPort
uid 5666,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5667,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,76625,750,77375"
)
tg (CPTG
uid 5668,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5669,0
va (VaSet
font "arial,8,0"
)
xt "-3900,76500,-1000,77500"
st "adc_otr"
ju 2
blo "-1000,77300"
)
)
thePort (LogicalPort
lang 10
m 1
decl (Decl
n "adc_otr"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 5
suid 7,0
)
)
)
*250 (CptPort
uid 5670,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5671,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,76625,-18000,77375"
)
tg (CPTG
uid 5672,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5673,0
va (VaSet
font "arial,8,0"
)
xt "-17000,76500,-11600,77500"
st "adc_otr_array"
blo "-17000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "adc_otr_array"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 3
suid 8,0
)
)
)
*251 (CptPort
uid 5674,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5675,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-18750,73625,-18000,74375"
)
tg (CPTG
uid 5676,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5677,0
va (VaSet
font "arial,8,0"
)
xt "-17000,73500,-14500,74500"
st "clk_ps"
blo "-17000,74300"
)
)
thePort (LogicalPort
lang 10
decl (Decl
n "clk_ps"
t "std_logic"
o 1
suid 9,0
)
)
)
]
shape (Rectangle
uid 5679,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-18000,73000,0,80000"
)
oxt "15000,6000,23000,11000"
ttg (MlTextGroup
uid 5680,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*252 (Text
uid 5681,0
va (VaSet
font "arial,8,1"
)
xt "900,77500,7100,78500"
st "FACT_FAD_lib"
blo "900,78300"
tm "BdLibraryNameMgr"
)
*253 (Text
uid 5682,0
va (VaSet
font "arial,8,1"
)
xt "900,78500,5700,79500"
st "adc_buffer"
blo "900,79300"
tm "CptNameMgr"
)
*254 (Text
uid 5683,0
va (VaSet
font "arial,8,1"
)
xt "900,79500,8500,80500"
st "I_main_adc_buffer"
blo "900,80300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5684,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5685,0
text (MLText
uid 5686,0
va (VaSet
font "Courier New,8,0"
)
xt "-38000,73300,-38000,73300"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 5687,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "-17750,78250,-16250,79750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*255 (Net
uid 5743,0
decl (Decl
n "config_start_spi"
t "std_logic"
o 46
suid 149,0
i "'0'"
)
declText (MLText
uid 5744,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,56200,-41500,57000"
st "SIGNAL config_start_spi       : std_logic                                    := '0'"
)
)
*256 (SaComponent
uid 5793,0
optionalChildren [
*257 (CptPort
uid 5753,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5754,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,106625,21000,107375"
)
tg (CPTG
uid 5755,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5756,0
va (VaSet
)
xt "22000,106500,23700,107500"
st "sclk"
blo "22000,107300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sclk"
t "std_logic"
o 8
suid 1,0
)
)
)
*258 (CptPort
uid 5761,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5762,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,108625,37750,109375"
)
tg (CPTG
uid 5763,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5764,0
va (VaSet
)
xt "32300,108500,36000,109500"
st "dac_array"
ju 2
blo "36000,109300"
)
)
thePort (LogicalPort
decl (Decl
n "dac_array"
t "dac_array_type"
o 3
suid 10,0
)
)
)
*259 (CptPort
uid 5765,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5766,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,106625,37750,107375"
)
tg (CPTG
uid 5767,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5768,0
va (VaSet
)
xt "30900,106500,36000,107500"
st "config_ready"
ju 2
blo "36000,107300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_ready"
t "std_logic"
o 4
suid 11,0
)
)
)
*260 (CptPort
uid 5769,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5770,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,104625,37750,105375"
)
tg (CPTG
uid 5771,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5772,0
va (VaSet
)
xt "31200,104500,36000,105500"
st "config_start"
ju 2
blo "36000,105300"
)
)
thePort (LogicalPort
decl (Decl
n "config_start"
t "std_logic"
o 2
suid 12,0
)
)
)
*261 (CptPort
uid 5773,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5774,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,101625,37750,102375"
)
tg (CPTG
uid 5775,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5776,0
va (VaSet
)
xt "30800,101500,36000,102500"
st "sensor_array"
ju 2
blo "36000,102300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_array"
t "sensor_array_type"
o 9
suid 13,0
)
)
)
*262 (CptPort
uid 5777,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5778,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,100625,37750,101375"
)
tg (CPTG
uid 5779,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5780,0
va (VaSet
)
xt "30700,100500,36000,101500"
st "sensor_ready"
ju 2
blo "36000,101300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_ready"
t "std_logic"
o 11
suid 14,0
)
)
)
*263 (CptPort
uid 5781,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5782,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,104625,21000,105375"
)
tg (CPTG
uid 5783,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5784,0
va (VaSet
)
xt "22000,104500,24800,105500"
st "dac_cs"
blo "22000,105300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dac_cs"
t "std_logic"
o 6
suid 15,0
)
)
)
*264 (CptPort
uid 5785,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5786,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,103625,21000,104375"
)
tg (CPTG
uid 5787,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5788,0
va (VaSet
)
xt "22000,103500,28500,104500"
st "sensor_cs : (3:0)"
blo "22000,104300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 10
suid 16,0
)
)
)
*265 (CptPort
uid 5789,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5790,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,100625,21000,101375"
)
tg (CPTG
uid 5791,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 5792,0
va (VaSet
)
xt "22000,100500,26200,101500"
st "clk_50MHz"
blo "22000,101300"
)
)
thePort (LogicalPort
decl (Decl
n "clk_50MHz"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 17,0
)
)
)
*266 (CptPort
uid 5986,0
ps "OnEdgeStrategy"
shape (Triangle
uid 5987,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "37000,105625,37750,106375"
)
tg (CPTG
uid 5988,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 5989,0
va (VaSet
)
xt "30400,105500,36000,106500"
st "config_started"
ju 2
blo "36000,106300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "config_started"
t "std_logic"
o 5
suid 18,0
i "'0'"
)
)
)
*267 (CptPort
uid 6154,0
ps "OnEdgeStrategy"
shape (Triangle
uid 6155,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,108625,21000,109375"
)
tg (CPTG
uid 6156,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6157,0
va (VaSet
)
xt "22000,108500,24000,109500"
st "mosi"
blo "22000,109300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "mosi"
t "std_logic"
o 7
suid 19,0
i "'0'"
)
)
)
*268 (CptPort
uid 6317,0
ps "OnEdgeStrategy"
shape (Diamond
uid 6318,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "20250,107625,21000,108375"
)
tg (CPTG
uid 6319,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6320,0
va (VaSet
)
xt "22000,107500,24000,108500"
st "miso"
blo "22000,108300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "miso"
t "std_logic"
preAdd 0
posAdd 0
o 12
suid 20,0
)
)
)
]
shape (Rectangle
uid 5794,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "21000,100000,37000,112000"
)
oxt "15000,12000,30000,26000"
ttg (MlTextGroup
uid 5795,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*269 (Text
uid 5796,0
va (VaSet
font "Arial,8,1"
)
xt "21200,112000,27400,113000"
st "FACT_FAD_lib"
blo "21200,112800"
tm "BdLibraryNameMgr"
)
*270 (Text
uid 5797,0
va (VaSet
font "Arial,8,1"
)
xt "21200,113000,26700,114000"
st "spi_interface"
blo "21200,113800"
tm "CptNameMgr"
)
*271 (Text
uid 5798,0
va (VaSet
font "Arial,8,1"
)
xt "21200,114000,30000,115000"
st "I_main_SPI_interface"
blo "21200,114800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 5799,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 5800,0
text (MLText
uid 5801,0
va (VaSet
font "Courier New,8,0"
)
xt "6000,100000,6000,100000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 5802,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "21250,110250,22750,111750"
iconName "BlockDiagram.png"
iconMaskName "BlockDiagram.msk"
ftype 1
)
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*272 (Net
uid 5811,0
decl (Decl
n "sclk"
t "std_logic"
o 23
suid 151,0
)
declText (MLText
uid 5812,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,35800,-66500,36600"
st "sclk                   : std_logic"
)
)
*273 (Net
uid 5819,0
decl (Decl
n "sio"
t "std_logic"
preAdd 0
posAdd 0
o 30
suid 152,0
)
declText (MLText
uid 5820,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,41400,-66500,42200"
st "sio                    : std_logic"
)
)
*274 (Net
uid 5827,0
decl (Decl
n "dac_cs"
t "std_logic"
o 17
suid 153,0
)
declText (MLText
uid 5828,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,31000,-66500,31800"
st "dac_cs                 : std_logic"
)
)
*275 (Net
uid 5835,0
decl (Decl
n "sensor_cs"
t "std_logic_vector"
b "(3 DOWNTO 0)"
o 24
suid 154,0
)
declText (MLText
uid 5836,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,36600,-56500,37400"
st "sensor_cs              : std_logic_vector(3 DOWNTO 0)"
)
)
*276 (PortIoOut
uid 5843,0
shape (CompositeShape
uid 5844,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5845,0
sl 0
ro 90
xt "10000,106625,11500,107375"
)
(Line
uid 5846,0
sl 0
ro 90
xt "11500,107000,12000,107000"
pts [
"12000,107000"
"11500,107000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5847,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5848,0
va (VaSet
)
xt "7300,106500,9000,107500"
st "sclk"
ju 2
blo "9000,107300"
tm "WireNameMgr"
)
)
)
*277 (PortIoInOut
uid 5849,0
shape (CompositeShape
uid 5850,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
uid 5851,0
sl 0
ro 180
xt "10000,107625,11500,108375"
)
(Line
uid 5852,0
sl 0
ro 180
xt "11500,108000,12000,108000"
pts [
"12000,108000"
"11500,108000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5853,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5854,0
va (VaSet
)
xt "7600,107500,9000,108500"
st "sio"
ju 2
blo "9000,108300"
tm "WireNameMgr"
)
)
)
*278 (PortIoOut
uid 5855,0
shape (CompositeShape
uid 5856,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5857,0
sl 0
ro 90
xt "10000,104625,11500,105375"
)
(Line
uid 5858,0
sl 0
ro 90
xt "11500,105000,12000,105000"
pts [
"12000,105000"
"11500,105000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5859,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5860,0
va (VaSet
)
xt "6200,104500,9000,105500"
st "dac_cs"
ju 2
blo "9000,105300"
tm "WireNameMgr"
)
)
)
*279 (PortIoOut
uid 5861,0
shape (CompositeShape
uid 5862,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 5863,0
sl 0
ro 90
xt "10000,103625,11500,104375"
)
(Line
uid 5864,0
sl 0
ro 90
xt "11500,104000,12000,104000"
pts [
"12000,104000"
"11500,104000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 5865,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5866,0
va (VaSet
)
xt "5100,103500,9000,104500"
st "sensor_cs"
ju 2
blo "9000,104300"
tm "WireNameMgr"
)
)
)
*280 (Net
uid 5948,0
decl (Decl
n "new_config"
t "std_logic"
o 60
suid 155,0
i "'0'"
)
declText (MLText
uid 5949,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,67400,-41500,68200"
st "SIGNAL new_config             : std_logic                                    := '0'"
)
)
*281 (Net
uid 5960,0
decl (Decl
n "config_started"
t "std_logic"
o 47
suid 156,0
)
declText (MLText
uid 5961,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,57000,-62500,57800"
st "SIGNAL config_started         : std_logic"
)
)
*282 (Net
uid 6012,0
decl (Decl
n "config_started_spi"
t "std_logic"
o 50
suid 159,0
i "'0'"
)
declText (MLText
uid 6013,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,59400,-41500,60200"
st "SIGNAL config_started_spi     : std_logic                                    := '0'"
)
)
*283 (Net
uid 6014,0
decl (Decl
n "config_started_cu"
t "std_logic"
o 48
suid 160,0
i "'0'"
)
declText (MLText
uid 6015,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,57800,-41500,58600"
st "SIGNAL config_started_cu      : std_logic                                    := '0'"
)
)
*284 (Net
uid 6016,0
decl (Decl
n "config_started_mm"
t "std_logic"
o 49
suid 161,0
)
declText (MLText
uid 6017,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,58600,-62500,59400"
st "SIGNAL config_started_mm      : std_logic"
)
)
*285 (Net
uid 6158,0
decl (Decl
n "mosi"
t "std_logic"
o 22
suid 162,0
i "'0'"
)
declText (MLText
uid 6159,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,35000,-45000,35800"
st "mosi                   : std_logic                                    := '0'"
)
)
*286 (PortIoOut
uid 6166,0
shape (CompositeShape
uid 6167,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 6168,0
sl 0
ro 90
xt "10000,108625,11500,109375"
)
(Line
uid 6169,0
sl 0
ro 90
xt "11500,109000,12000,109000"
pts [
"12000,109000"
"11500,109000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 6170,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6171,0
va (VaSet
)
xt "7000,108500,9000,109500"
st "mosi"
ju 2
blo "9000,109300"
tm "WireNameMgr"
)
)
)
*287 (Net
uid 6360,0
decl (Decl
n "denable"
t "std_logic"
eolc "-- default domino wave off"
posAdd 0
o 18
suid 166,0
i "'0'"
)
declText (MLText
uid 6361,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,31800,-31500,32600"
st "denable                : std_logic                                    := '0' -- default domino wave off"
)
)
*288 (PortIoOut
uid 6368,0
shape (CompositeShape
uid 6369,0
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
uid 6370,0
sl 0
ro 270
xt "153500,74625,155000,75375"
)
(Line
uid 6371,0
sl 0
ro 270
xt "153000,75000,153500,75000"
pts [
"153000,75000"
"153500,75000"
]
)
]
)
stc 0
sf 1
tg (WTG
uid 6372,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6373,0
va (VaSet
)
xt "156000,74500,159000,75500"
st "denable"
blo "156000,75300"
tm "WireNameMgr"
)
)
)
*289 (Net
uid 6450,0
decl (Decl
n "dwrite_enable"
t "std_logic"
o 59
suid 167,0
i "'1'"
)
declText (MLText
uid 6451,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,66600,-41500,67400"
st "SIGNAL dwrite_enable          : std_logic                                    := '1'"
)
)
*290 (MWC
uid 6529,0
optionalChildren [
*291 (CptPort
uid 6501,0
optionalChildren [
*292 (Line
uid 6505,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "1000,60000,2000,60000"
pts [
"1000,60000"
"2000,60000"
]
)
*293 (Property
uid 6506,0
pclass "_MW_GEOM_"
pname "fixed"
ptn "String"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 6502,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "250,59625,1000,60375"
)
tg (CPTG
uid 6503,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 6504,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "21669,299342,23469,300342"
st "dout"
blo "21669,300142"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "dout"
t "std_logic"
o 20
suid 1,0
i "'1'"
)
)
)
*294 (CptPort
uid 6507,0
optionalChildren [
*295 (Line
uid 6511,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "6000,59000,7000,59000"
pts [
"7000,59000"
"6000,59000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 6508,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "7000,58625,7750,59375"
)
tg (CPTG
uid 6509,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6510,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "24635,298294,26435,299294"
st "din0"
ju 2
blo "26435,299094"
)
)
thePort (LogicalPort
decl (Decl
n "din0"
t "std_logic"
o 58
suid 2,0
i "'1'"
)
)
)
*296 (CptPort
uid 6512,0
optionalChildren [
*297 (Line
uid 6516,0
layer 5
sl 0
va (VaSet
vasetType 3
)
xt "6000,61000,7000,61000"
pts [
"7000,61000"
"6000,61000"
]
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 6513,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,65535"
)
xt "7000,60625,7750,61375"
)
tg (CPTG
uid 6514,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 6515,0
sl 0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "24750,300700,26550,301700"
st "din1"
ju 2
blo "26550,301500"
)
)
thePort (LogicalPort
decl (Decl
n "din1"
t "std_logic"
o 59
suid 3,0
i "'1'"
)
)
)
*298 (CommentGraphic
uid 6517,0
optionalChildren [
*299 (Property
uid 6519,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"6000,62000"
"6000,62000"
]
uid 6518,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "6000,62000,6000,62000"
)
oxt "11000,10000,11000,10000"
)
*300 (CommentGraphic
uid 6520,0
optionalChildren [
*301 (Property
uid 6522,0
pclass "_MW_GEOM_"
pname "expand"
ptn "String"
)
]
shape (PolyLine2D
pts [
"6000,58000"
"6000,58000"
]
uid 6521,0
layer 0
sl 0
va (VaSet
vasetType 1
transparent 1
fg "49152,49152,49152"
)
xt "6000,58000,6000,58000"
)
oxt "11000,6000,11000,6000"
)
*302 (Grouping
uid 6523,0
optionalChildren [
*303 (CommentGraphic
uid 6525,0
shape (PolyLine2D
pts [
"4000,58000"
"6000,58000"
"6000,62000"
"4000,62000"
]
uid 6526,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "4000,58000,6000,62000"
)
oxt "9000,6000,11000,10000"
)
*304 (CommentGraphic
uid 6527,0
shape (Arc2D
pts [
"4000,62000"
"2000,60000"
"4000,58000"
]
uid 6528,0
layer 0
sl 0
va (VaSet
vasetType 1
fg "0,65535,65535"
lineColor "26368,26368,26368"
)
xt "2000,58000,4000,62000"
)
oxt "7000,6000,9000,10000"
)
]
shape (GroupingShape
uid 6524,0
sl 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 2
)
xt "2000,58000,6000,62000"
)
oxt "7000,6000,11000,10000"
)
]
shape (Rectangle
uid 6530,0
va (VaSet
vasetType 1
transparent 1
fg "65535,65535,65535"
lineWidth -1
)
xt "1000,58000,7000,62000"
fos 1
)
showPorts 0
oxt "6000,6000,12000,10000"
ttg (MlTextGroup
uid 6531,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*305 (Text
uid 6532,0
va (VaSet
isHidden 1
font "arial,8,0"
)
xt "3500,58500,8300,59500"
st "moduleware"
blo "3500,59300"
)
*306 (Text
uid 6533,0
va (VaSet
font "arial,8,0"
)
xt "3500,59500,5100,60500"
st "and"
blo "3500,60300"
)
*307 (Text
uid 6534,0
va (VaSet
font "arial,8,0"
)
xt "3500,60500,4500,61500"
st "I5"
blo "3500,61300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 6535,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 6536,0
text (MLText
uid 6537,0
va (VaSet
font "arial,8,0"
)
xt "-14000,49000,-14000,49000"
)
header ""
)
elements [
]
)
sed 1
awe 1
portVis (PortSigDisplay
sN 0
sTC 0
selT 0
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
de 1
visOptions (mwParamsVisibilityOptions
)
)
*308 (Net
uid 6544,0
decl (Decl
n "dwrite"
t "std_logic"
o 58
suid 169,0
i "'1'"
)
declText (MLText
uid 6545,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,65800,-41500,66600"
st "SIGNAL dwrite                 : std_logic                                    := '1'"
)
)
*309 (SaComponent
uid 8277,0
optionalChildren [
*310 (CptPort
uid 8246,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8247,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "76250,43625,77000,44375"
)
tg (CPTG
uid 8248,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8249,0
va (VaSet
font "arial,8,0"
)
xt "78000,43500,79700,44500"
st "clka"
blo "78000,44300"
)
)
thePort (LogicalPort
decl (Decl
n "clka"
t "std_logic"
preAdd 0
posAdd 0
o 1
suid 1,0
)
)
)
*311 (CptPort
uid 8250,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8251,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "76250,49625,77000,50375"
)
tg (CPTG
uid 8252,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8253,0
va (VaSet
font "arial,8,0"
)
xt "78000,49500,82800,50500"
st "dina : (63:0)"
blo "78000,50300"
)
)
thePort (LogicalPort
decl (Decl
n "dina"
t "std_logic_VECTOR"
b "(63 downto 0)"
preAdd 0
posAdd 0
o 2
suid 2,0
)
)
)
*312 (CptPort
uid 8254,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8255,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "76250,48625,77000,49375"
)
tg (CPTG
uid 8256,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8257,0
va (VaSet
font "arial,8,0"
)
xt "78000,48500,83300,49500"
st "addra : (14:0)"
blo "78000,49300"
)
)
thePort (LogicalPort
decl (Decl
n "addra"
t "std_logic_VECTOR"
b "(14 downto 0)"
preAdd 0
posAdd 0
o 3
suid 3,0
)
)
)
*313 (CptPort
uid 8258,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8259,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "76250,47625,77000,48375"
)
tg (CPTG
uid 8260,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 8261,0
va (VaSet
font "arial,8,0"
)
xt "78000,47500,82300,48500"
st "wea : (0:0)"
blo "78000,48300"
)
)
thePort (LogicalPort
decl (Decl
n "wea"
t "std_logic_VECTOR"
b "(0 downto 0)"
preAdd 0
posAdd 0
o 4
suid 4,0
)
)
)
*314 (CptPort
uid 8262,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8263,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,43625,91750,44375"
)
tg (CPTG
uid 8264,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8265,0
va (VaSet
font "arial,8,0"
)
xt "88300,43500,90000,44500"
st "clkb"
ju 2
blo "90000,44300"
)
)
thePort (LogicalPort
decl (Decl
n "clkb"
t "std_logic"
preAdd 0
posAdd 0
o 5
suid 5,0
)
)
)
*315 (CptPort
uid 8266,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8267,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,48625,91750,49375"
)
tg (CPTG
uid 8268,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8269,0
va (VaSet
font "arial,8,0"
)
xt "84700,48500,90000,49500"
st "addrb : (16:0)"
ju 2
blo "90000,49300"
)
)
thePort (LogicalPort
decl (Decl
n "addrb"
t "std_logic_VECTOR"
b "(16 downto 0)"
preAdd 0
posAdd 0
o 6
suid 6,0
)
)
)
*316 (CptPort
uid 8270,0
ps "OnEdgeStrategy"
shape (Triangle
uid 8271,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "91000,49625,91750,50375"
)
tg (CPTG
uid 8272,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 8273,0
va (VaSet
font "arial,8,0"
)
xt "84800,49500,90000,50500"
st "doutb : (15:0)"
ju 2
blo "90000,50300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "doutb"
t "std_logic_VECTOR"
b "(15 downto 0)"
preAdd 0
posAdd 0
o 7
suid 7,0
)
)
)
]
shape (Rectangle
uid 8278,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "77000,42000,91000,52000"
)
oxt "30000,7000,40000,21000"
ttg (MlTextGroup
uid 8279,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*317 (Text
uid 8280,0
va (VaSet
font "arial,8,1"
)
xt "77200,52000,83400,53000"
st "FACT_FAD_lib"
blo "77200,52800"
tm "BdLibraryNameMgr"
)
*318 (Text
uid 8281,0
va (VaSet
font "arial,8,1"
)
xt "77200,53000,89200,54000"
st "dataRAM_64b_16b_width14_5"
blo "77200,53800"
tm "CptNameMgr"
)
*319 (Text
uid 8282,0
va (VaSet
font "arial,8,1"
)
xt "77200,54000,79000,55000"
st "U_4"
blo "77200,54800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 8283,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 8284,0
text (MLText
uid 8285,0
va (VaSet
font "Courier New,8,0"
)
xt "76500,41000,76500,41000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 8286,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "77250,50250,78750,51750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
sIVOD 1
)
archFileType "UNKNOWN"
)
*320 (Net
uid 8414,0
lang 2
decl (Decl
n "wiz_ack"
t "std_logic"
o 81
suid 183,0
)
declText (MLText
uid 8415,0
va (VaSet
font "Courier New,8,0"
)
xt "-85000,77800,-62500,78600"
st "SIGNAL wiz_ack                : std_logic"
)
)
*321 (Wire
uid 322,0
shape (OrthoPolyLine
uid 323,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,48000,76250,48000"
pts [
"40750,48000"
"55000,48000"
"76250,48000"
]
)
start &26
end &313
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 324,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 325,0
va (VaSet
)
xt "42000,47000,47800,48000"
st "write_ea : (0:0)"
blo "42000,47800"
tm "WireNameMgr"
)
)
on &2
)
*322 (Wire
uid 328,0
shape (OrthoPolyLine
uid 329,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,49000,76250,49000"
pts [
"40750,49000"
"55000,49000"
"76250,49000"
]
)
start &25
end &312
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 330,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 331,0
va (VaSet
)
xt "42000,48000,56500,49000"
st "addr_out : (RAMADDRWIDTH64b-1:0)"
blo "42000,48800"
tm "WireNameMgr"
)
)
on &3
)
*323 (Wire
uid 334,0
shape (OrthoPolyLine
uid 335,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,50000,76250,50000"
pts [
"40750,50000"
"55000,50000"
"76250,50000"
]
)
start &24
end &311
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 336,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 337,0
va (VaSet
)
xt "42000,49000,48200,50000"
st "data_out : (63:0)"
blo "42000,49800"
tm "WireNameMgr"
)
)
on &4
)
*324 (Wire
uid 364,0
shape (OrthoPolyLine
uid 365,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,49000,126250,54000"
pts [
"126250,54000"
"113000,54000"
"113000,49000"
"91750,49000"
]
)
start &79
end &315
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 367,0
va (VaSet
)
xt "94000,48000,109000,49000"
st "ram_addr : (RAMADDRWIDTH64b+1:0)"
blo "94000,48800"
tm "WireNameMgr"
)
)
on &5
)
*325 (Wire
uid 370,0
shape (OrthoPolyLine
uid 371,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "91750,50000,126250,55000"
pts [
"126250,55000"
"112000,55000"
"112000,50000"
"91750,50000"
]
)
start &78
end &316
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 372,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 373,0
va (VaSet
)
xt "95000,50000,101500,51000"
st "ram_data : (15:0)"
blo "95000,50800"
tm "WireNameMgr"
)
)
on &6
)
*326 (Wire
uid 376,0
shape (OrthoPolyLine
uid 377,0
va (VaSet
vasetType 3
)
xt "148750,52000,153000,52000"
pts [
"148750,52000"
"153000,52000"
]
)
start &69
end &14
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 380,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 381,0
va (VaSet
isHidden 1
)
xt "150000,51000,153600,52000"
st "wiz_reset"
blo "150000,51800"
tm "WireNameMgr"
)
)
on &7
)
*327 (Wire
uid 384,0
shape (OrthoPolyLine
uid 385,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "148750,60000,153000,60000"
pts [
"148750,60000"
"153000,60000"
]
)
start &70
end &15
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 388,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 389,0
va (VaSet
isHidden 1
)
xt "150000,59000,153400,60000"
st "wiz_addr"
blo "150000,59800"
tm "WireNameMgr"
)
)
on &8
)
*328 (Wire
uid 392,0
shape (OrthoPolyLine
uid 393,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "148750,61000,153000,61000"
pts [
"148750,61000"
"153000,61000"
]
)
start &71
end &16
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 396,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 397,0
va (VaSet
isHidden 1
)
xt "150000,60000,153300,61000"
st "wiz_data"
blo "150000,60800"
tm "WireNameMgr"
)
)
on &9
)
*329 (Wire
uid 400,0
shape (OrthoPolyLine
uid 401,0
va (VaSet
vasetType 3
)
xt "148750,53000,153000,53000"
pts [
"148750,53000"
"153000,53000"
]
)
start &72
end &17
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 404,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 405,0
va (VaSet
isHidden 1
)
xt "150000,52000,152700,53000"
st "wiz_cs"
blo "150000,52800"
tm "WireNameMgr"
)
)
on &10
)
*330 (Wire
uid 408,0
shape (OrthoPolyLine
uid 409,0
va (VaSet
vasetType 3
)
xt "148750,54000,153000,54000"
pts [
"148750,54000"
"153000,54000"
]
)
start &73
end &18
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 412,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 413,0
va (VaSet
isHidden 1
)
xt "150000,53000,152700,54000"
st "wiz_wr"
blo "150000,53800"
tm "WireNameMgr"
)
)
on &11
)
*331 (Wire
uid 424,0
shape (OrthoPolyLine
uid 425,0
va (VaSet
vasetType 3
)
xt "148750,55000,153000,55000"
pts [
"148750,55000"
"153000,55000"
]
)
start &74
end &20
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 428,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 429,0
va (VaSet
isHidden 1
)
xt "150000,54000,152600,55000"
st "wiz_rd"
blo "150000,54800"
tm "WireNameMgr"
)
)
on &12
)
*332 (Wire
uid 432,0
shape (OrthoPolyLine
uid 433,0
va (VaSet
vasetType 3
)
xt "148750,56000,153000,56000"
pts [
"153000,56000"
"148750,56000"
]
)
start &21
end &75
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 436,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 437,0
va (VaSet
isHidden 1
)
xt "150000,55000,152700,56000"
st "wiz_int"
blo "150000,55800"
tm "WireNameMgr"
)
)
on &13
)
*333 (Wire
uid 1411,0
shape (OrthoPolyLine
uid 1412,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-26000,86000,18250,86000"
pts [
"-26000,86000"
"18250,86000"
]
)
start &149
end &28
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1415,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1416,0
va (VaSet
)
xt "-24000,85000,-20700,86000"
st "board_id"
blo "-24000,85800"
tm "WireNameMgr"
)
)
on &64
)
*334 (Wire
uid 1425,0
optionalChildren [
*335 (BdJunction
uid 4391,0
ps "OnConnectorStrategy"
shape (Circle
uid 4392,0
va (VaSet
vasetType 1
)
xt "-22400,68600,-21600,69400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 1426,0
va (VaSet
vasetType 3
)
xt "-26000,69000,18250,69000"
pts [
"-26000,69000"
"18250,69000"
]
)
start &66
end &30
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1429,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1430,0
va (VaSet
isHidden 1
)
xt "5000,63000,7800,64000"
st "trigger"
blo "5000,63800"
tm "WireNameMgr"
)
)
on &65
)
*336 (Wire
uid 1682,0
shape (OrthoPolyLine
uid 1683,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-26000,87000,18250,87000"
pts [
"-26000,87000"
"18250,87000"
]
)
start &150
end &31
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1686,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1687,0
va (VaSet
)
xt "-24000,86000,-20900,87000"
st "crate_id"
blo "-24000,86800"
tm "WireNameMgr"
)
)
on &100
)
*337 (Wire
uid 1983,0
shape (OrthoPolyLine
uid 1984,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-6250,64000,18250,68000"
pts [
"-6250,64000"
"6000,64000"
"6000,68000"
"18250,68000"
]
)
start &102
end &29
sat 32
eat 32
sty 1
st 0
sf 1
tg (WTG
uid 1985,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1986,0
va (VaSet
)
xt "11000,67000,17800,68000"
st "trigger_id : (47:0)"
blo "11000,67800"
tm "WireNameMgr"
)
)
on &108
)
*338 (Wire
uid 2299,0
shape (OrthoPolyLine
uid 2300,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,63000,71250,70000"
pts [
"71250,70000"
"67000,70000"
"67000,63000"
"40750,63000"
]
)
start &111
end &27
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2303,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2304,0
va (VaSet
)
xt "42000,62000,58700,63000"
st "ram_start_addr : (RAMADDRWIDTH64b-1:0)"
blo "42000,62800"
tm "WireNameMgr"
)
)
on &109
)
*339 (Wire
uid 2470,0
shape (OrthoPolyLine
uid 2471,0
va (VaSet
vasetType 3
)
xt "103750,68000,126250,68000"
pts [
"103750,68000"
"115000,68000"
"126250,68000"
]
)
start &118
end &81
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2472,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2473,0
va (VaSet
)
xt "104000,67000,107400,68000"
st "wiz_busy"
blo "104000,67800"
tm "WireNameMgr"
)
)
on &132
)
*340 (Wire
uid 2476,0
shape (OrthoPolyLine
uid 2477,0
va (VaSet
vasetType 3
)
xt "103750,69000,126250,69000"
pts [
"103750,69000"
"115000,69000"
"126250,69000"
]
)
start &121
end &80
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2478,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2479,0
va (VaSet
)
xt "104000,68000,109100,69000"
st "wiz_write_ea"
blo "104000,68800"
tm "WireNameMgr"
)
)
on &133
)
*341 (Wire
uid 2482,0
shape (OrthoPolyLine
uid 2483,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "103750,70000,126250,70000"
pts [
"103750,70000"
"115000,70000"
"126250,70000"
]
)
start &124
end &76
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2484,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2485,0
va (VaSet
)
xt "104000,69000,113400,70000"
st "wiz_write_length : (16:0)"
blo "104000,69800"
tm "WireNameMgr"
)
)
on &134
)
*342 (Wire
uid 2488,0
shape (OrthoPolyLine
uid 2489,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "103750,71000,126250,71000"
pts [
"103750,71000"
"115000,71000"
"126250,71000"
]
)
start &120
end &77
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2490,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2491,0
va (VaSet
)
xt "104000,70000,122800,71000"
st "wiz_ram_start_addr : (RAMADDRWIDTH64b+1:0)"
blo "104000,70800"
tm "WireNameMgr"
)
)
on &135
)
*343 (Wire
uid 2494,0
shape (OrthoPolyLine
uid 2495,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "103750,72000,126250,72000"
pts [
"103750,72000"
"115000,72000"
"126250,72000"
]
)
start &119
end &82
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2496,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2497,0
va (VaSet
)
xt "104000,71000,115800,72000"
st "wiz_number_of_channels : (3:0)"
blo "104000,71800"
tm "WireNameMgr"
)
)
on &136
)
*344 (Wire
uid 2500,0
shape (OrthoPolyLine
uid 2501,0
va (VaSet
vasetType 3
)
xt "103750,73000,126250,73000"
pts [
"103750,73000"
"115000,73000"
"126250,73000"
]
)
start &122
end &83
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2502,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2503,0
va (VaSet
)
xt "104000,72000,109500,73000"
st "wiz_write_end"
blo "104000,72800"
tm "WireNameMgr"
)
)
on &137
)
*345 (Wire
uid 2506,0
shape (OrthoPolyLine
uid 2507,0
va (VaSet
vasetType 3
)
xt "103750,74000,126250,74000"
pts [
"103750,74000"
"115000,74000"
"126250,74000"
]
)
start &123
end &84
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2508,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2509,0
va (VaSet
)
xt "104000,73000,110600,74000"
st "wiz_write_header"
blo "104000,73800"
tm "WireNameMgr"
)
)
on &138
)
*346 (Wire
uid 2576,0
shape (OrthoPolyLine
uid 2577,0
va (VaSet
vasetType 3
)
xt "40750,64000,71250,71000"
pts [
"40750,64000"
"66000,64000"
"66000,71000"
"71250,71000"
]
)
start &32
end &115
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2578,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2579,0
va (VaSet
)
xt "42000,63000,47300,64000"
st "ram_write_ea"
blo "42000,63800"
tm "WireNameMgr"
)
)
on &139
)
*347 (Wire
uid 2582,0
shape (OrthoPolyLine
uid 2583,0
va (VaSet
vasetType 3
)
xt "40750,65000,71250,72000"
pts [
"40750,65000"
"65000,65000"
"65000,72000"
"71250,72000"
]
)
start &33
end &116
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2584,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2585,0
va (VaSet
)
xt "42000,64000,48300,65000"
st "ram_write_ready"
blo "42000,64800"
tm "WireNameMgr"
)
)
on &140
)
*348 (Wire
uid 2588,0
shape (OrthoPolyLine
uid 2589,0
va (VaSet
vasetType 3
)
xt "40750,70000,71250,75000"
pts [
"40750,70000"
"64000,70000"
"64000,75000"
"71250,75000"
]
)
start &53
end &114
ss 0
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2590,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2591,0
va (VaSet
)
xt "41000,69000,45800,70000"
st "config_start"
blo "41000,69800"
tm "WireNameMgr"
)
)
on &141
)
*349 (Wire
uid 2594,0
shape (OrthoPolyLine
uid 2595,0
va (VaSet
vasetType 3
)
xt "40750,72000,71250,77000"
pts [
"40750,72000"
"62000,72000"
"62000,77000"
"71250,77000"
]
)
start &49
end &113
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2596,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2597,0
va (VaSet
)
xt "41000,71000,46100,72000"
st "config_ready"
blo "41000,71800"
tm "WireNameMgr"
)
)
on &142
)
*350 (Wire
uid 2600,0
shape (OrthoPolyLine
uid 2601,0
va (VaSet
vasetType 3
)
xt "40750,74000,71250,78000"
pts [
"40750,74000"
"61000,74000"
"61000,78000"
"71250,78000"
]
)
start &34
end &117
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 2602,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2603,0
va (VaSet
)
xt "41000,73000,44000,74000"
st "roi_max"
blo "41000,73800"
tm "WireNameMgr"
)
)
on &143
)
*351 (Wire
uid 2642,0
shape (OrthoPolyLine
uid 2643,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "40750,75000,71250,79000"
pts [
"40750,75000"
"60000,75000"
"60000,79000"
"71250,79000"
]
)
start &36
end &126
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 2644,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2645,0
va (VaSet
)
xt "41000,74000,50100,75000"
st "package_length : (15:0)"
blo "41000,74800"
tm "WireNameMgr"
)
)
on &144
)
*352 (Wire
uid 2778,0
shape (OrthoPolyLine
uid 2779,0
va (VaSet
vasetType 3
)
xt "-26000,82000,18250,82000"
pts [
"18250,82000"
"-26000,82000"
]
)
start &37
end &146
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2782,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2783,0
va (VaSet
isHidden 1
)
xt "-20000,76000,-16800,77000"
st "adc_oeb"
blo "-20000,76800"
tm "WireNameMgr"
)
)
on &145
)
*353 (Wire
uid 2786,0
shape (OrthoPolyLine
uid 2787,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-26000,77000,-18750,77000"
pts [
"-26000,77000"
"-18750,77000"
]
)
start &147
end &250
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 2790,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2791,0
va (VaSet
isHidden 1
)
xt "-57000,70000,-51600,71000"
st "adc_otr_array"
blo "-57000,70800"
tm "WireNameMgr"
)
)
on &176
)
*354 (Wire
uid 2876,0
shape (OrthoPolyLine
uid 2877,0
va (VaSet
vasetType 3
)
xt "-22000,64000,-18750,69000"
pts [
"-22000,69000"
"-22000,64000"
"-18750,64000"
]
)
start &335
end &103
es 0
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 2880,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 2881,0
ro 270
va (VaSet
)
xt "-23000,64200,-22000,67000"
st "trigger"
blo "-22200,67000"
tm "WireNameMgr"
)
)
on &65
)
*355 (Wire
uid 3888,0
optionalChildren [
*356 (BdJunction
uid 4230,0
ps "OnConnectorStrategy"
shape (Circle
uid 4231,0
va (VaSet
vasetType 1
)
xt "4600,18600,5400,19400"
radius 400
)
)
*357 (BdJunction
uid 4244,0
ps "OnConnectorStrategy"
shape (Circle
uid 4245,0
va (VaSet
vasetType 1
)
xt "108600,18600,109400,19400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 3889,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "-1250,19000,126250,52000"
pts [
"-1250,19000"
"123000,19000"
"123000,52000"
"126250,52000"
]
)
start &166
end &68
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3890,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3891,0
va (VaSet
)
xt "750,18000,3850,19000"
st "CLK_50"
blo "750,18800"
tm "WireNameMgr"
)
)
on &164
)
*358 (Wire
uid 3984,0
shape (OrthoPolyLine
uid 3985,0
va (VaSet
vasetType 3
lineColor "49152,0,0"
)
xt "-26000,23000,2000,31000"
pts [
"-26000,31000"
"2000,31000"
"2000,23000"
"-1250,23000"
]
)
start &163
end &168
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 3986,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 3987,0
va (VaSet
isHidden 1
)
xt "-27000,32000,-22500,33000"
st "CLK_25_PS"
blo "-27000,32800"
tm "WireNameMgr"
)
)
on &162
)
*359 (Wire
uid 4042,0
shape (OrthoPolyLine
uid 4043,0
va (VaSet
vasetType 3
)
xt "-26000,19000,-20750,19000"
pts [
"-26000,19000"
"-20750,19000"
]
)
start &1
end &169
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4044,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4045,0
va (VaSet
isHidden 1
)
xt "-25000,32000,-23100,33000"
st "CLK"
blo "-25000,32800"
tm "WireNameMgr"
)
)
on &175
)
*360 (Wire
uid 4226,0
shape (OrthoPolyLine
uid 4227,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "-26000,19000,5000,34000"
pts [
"-26000,34000"
"5000,34000"
"5000,19000"
]
)
start &174
end &356
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4228,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4229,0
va (VaSet
isHidden 1
)
xt "-27000,30000,-23900,31000"
st "CLK_50"
blo "-27000,30800"
tm "WireNameMgr"
)
)
on &164
)
*361 (Wire
uid 4240,0
shape (OrthoPolyLine
uid 4241,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "91750,19000,109000,44000"
pts [
"91750,44000"
"109000,44000"
"109000,19000"
]
)
start &314
end &357
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4242,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4243,0
va (VaSet
)
xt "93000,44000,96100,45000"
st "CLK_50"
blo "93000,44800"
tm "WireNameMgr"
)
)
on &164
)
*362 (Wire
uid 4272,0
shape (OrthoPolyLine
uid 4273,0
va (VaSet
vasetType 3
)
xt "-26000,76000,-18750,76000"
pts [
"-26000,76000"
"-18750,76000"
]
)
start &178
end &247
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4274,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4275,0
va (VaSet
isHidden 1
)
xt "-56000,70000,-50100,71000"
st "adc_data_array"
blo "-56000,70800"
tm "WireNameMgr"
)
)
on &177
)
*363 (Wire
uid 4401,0
shape (OrthoPolyLine
uid 4402,0
va (VaSet
vasetType 3
)
xt "1750,53000,18250,53000"
pts [
"18250,53000"
"1750,53000"
]
)
start &40
end &197
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4403,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4404,0
va (VaSet
)
xt "13250,52000,17650,53000"
st "drs_clk_en"
blo "13250,52800"
tm "WireNameMgr"
)
)
on &179
)
*364 (Wire
uid 4407,0
shape (OrthoPolyLine
uid 4408,0
va (VaSet
vasetType 3
)
xt "1750,52000,18250,52000"
pts [
"18250,52000"
"1750,52000"
]
)
start &44
end &203
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4409,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4410,0
va (VaSet
)
xt "11250,51000,17650,52000"
st "drs_s_cell_array"
blo "11250,51800"
tm "WireNameMgr"
)
)
on &180
)
*365 (Wire
uid 4419,0
shape (OrthoPolyLine
uid 4420,0
va (VaSet
vasetType 3
)
xt "1750,50000,18250,50000"
pts [
"18250,50000"
"1750,50000"
]
)
start &42
end &198
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4421,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4422,0
va (VaSet
)
xt "11250,49000,17450,50000"
st "drs_read_s_cell"
blo "11250,49800"
tm "WireNameMgr"
)
)
on &181
)
*366 (Wire
uid 4537,0
shape (OrthoPolyLine
uid 4538,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "-26000,57000,18250,57000"
pts [
"18250,57000"
"-26000,57000"
]
)
start &39
end &184
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4541,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4542,0
va (VaSet
isHidden 1
)
xt "-20000,56000,-14100,57000"
st "drs_channel_id"
blo "-20000,56800"
tm "WireNameMgr"
)
)
on &182
)
*367 (Wire
uid 4545,0
shape (OrthoPolyLine
uid 4546,0
va (VaSet
vasetType 3
)
xt "-26000,60000,1000,60000"
pts [
"1000,60000"
"-26000,60000"
]
)
start &291
end &185
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4549,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4550,0
va (VaSet
)
xt "-18000,59000,-13700,60000"
st "drs_dwrite"
blo "-18000,59800"
tm "WireNameMgr"
)
)
on &183
)
*368 (Wire
uid 4671,0
shape (OrthoPolyLine
uid 4672,0
va (VaSet
vasetType 3
)
xt "-26000,47000,-18750,47000"
pts [
"-26000,47000"
"-18750,47000"
]
)
start &190
end &199
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4675,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4676,0
va (VaSet
isHidden 1
)
xt "-25000,46000,-19600,47000"
st "SROUT_in_0"
blo "-25000,46800"
tm "WireNameMgr"
)
)
on &186
)
*369 (Wire
uid 4679,0
shape (OrthoPolyLine
uid 4680,0
va (VaSet
vasetType 3
)
xt "-26000,48000,-18750,48000"
pts [
"-26000,48000"
"-18750,48000"
]
)
start &191
end &200
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4683,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4684,0
va (VaSet
isHidden 1
)
xt "-25000,47000,-19600,48000"
st "SROUT_in_1"
blo "-25000,47800"
tm "WireNameMgr"
)
)
on &187
)
*370 (Wire
uid 4687,0
shape (OrthoPolyLine
uid 4688,0
va (VaSet
vasetType 3
)
xt "-26000,49000,-18750,49000"
pts [
"-26000,49000"
"-18750,49000"
]
)
start &192
end &201
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4691,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4692,0
va (VaSet
isHidden 1
)
xt "-25000,48000,-19600,49000"
st "SROUT_in_2"
blo "-25000,48800"
tm "WireNameMgr"
)
)
on &188
)
*371 (Wire
uid 4695,0
shape (OrthoPolyLine
uid 4696,0
va (VaSet
vasetType 3
)
xt "-26000,50000,-18750,50000"
pts [
"-26000,50000"
"-18750,50000"
]
)
start &193
end &202
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4699,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4700,0
va (VaSet
isHidden 1
)
xt "-25000,49000,-19600,50000"
st "SROUT_in_3"
blo "-25000,49800"
tm "WireNameMgr"
)
)
on &189
)
*372 (Wire
uid 4743,0
shape (OrthoPolyLine
uid 4744,0
va (VaSet
vasetType 3
)
xt "1750,51000,18250,51000"
pts [
"1750,51000"
"18250,51000"
]
)
start &204
end &43
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 4747,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4748,0
va (VaSet
)
xt "3750,50000,12550,51000"
st "drs_read_s_cell_ready"
blo "3750,50800"
tm "WireNameMgr"
)
)
on &194
)
*373 (Wire
uid 4757,0
optionalChildren [
*374 (BdJunction
uid 6076,0
ps "OnConnectorStrategy"
shape (Circle
uid 6077,0
va (VaSet
vasetType 1
)
xt "14600,37600,15400,38400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 4758,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "-22000,38000,15000,45000"
pts [
"-18750,45000"
"-22000,45000"
"-22000,38000"
"15000,38000"
]
)
start &196
end *375 (BdJunction
uid 6080,0
ps "OnConnectorStrategy"
shape (Circle
uid 6081,0
va (VaSet
vasetType 1
)
xt "14600,37600,15400,38400"
radius 400
)
)
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4759,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4760,0
va (VaSet
)
xt "-22750,44000,-19650,45000"
st "CLK_25"
blo "-22750,44800"
tm "WireNameMgr"
)
)
on &173
)
*376 (Wire
uid 4948,0
shape (OrthoPolyLine
uid 4949,0
va (VaSet
vasetType 3
)
xt "-26000,51000,-18750,51000"
pts [
"-18750,51000"
"-26000,51000"
]
)
start &205
end &211
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4952,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4953,0
va (VaSet
isHidden 1
)
xt "-24000,50000,-19800,51000"
st "RSRLOAD"
blo "-24000,50800"
tm "WireNameMgr"
)
)
on &210
)
*377 (Wire
uid 4962,0
shape (OrthoPolyLine
uid 4963,0
va (VaSet
vasetType 3
)
xt "-26000,52000,-18750,52000"
pts [
"-18750,52000"
"-26000,52000"
]
)
start &206
end &213
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 4966,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 4967,0
va (VaSet
isHidden 1
)
xt "-23000,51000,-20000,52000"
st "SRCLK"
blo "-23000,51800"
tm "WireNameMgr"
)
)
on &212
)
*378 (Wire
uid 5090,0
shape (OrthoPolyLine
uid 5091,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "92750,79000,126250,100000"
pts [
"126250,79000"
"116000,79000"
"116000,100000"
"92750,100000"
]
)
start &87
end &216
sat 32
eat 32
sty 1
st 0
sf 1
tg (WTG
uid 5094,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5095,0
va (VaSet
)
xt "119000,78000,126000,79000"
st "config_addr : (7:0)"
blo "119000,78800"
tm "WireNameMgr"
)
)
on &230
)
*379 (Wire
uid 5098,0
shape (OrthoPolyLine
uid 5099,0
va (VaSet
vasetType 3
)
xt "92750,102000,103000,102000"
pts [
"92750,102000"
"103000,102000"
]
)
start &217
sat 32
eat 16
st 0
sf 1
tg (WTG
uid 5102,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5103,0
va (VaSet
)
xt "94000,101000,100600,102000"
st "config_data_valid"
blo "94000,101800"
tm "WireNameMgr"
)
)
on &231
)
*380 (Wire
uid 5106,0
shape (OrthoPolyLine
uid 5107,0
va (VaSet
vasetType 3
)
xt "92750,84000,126250,106000"
pts [
"92750,106000"
"121000,106000"
"121000,84000"
"126250,84000"
]
)
start &218
end &88
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5110,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5111,0
va (VaSet
)
xt "94750,105000,99550,106000"
st "config_busy"
blo "94750,105800"
tm "WireNameMgr"
)
)
on &232
)
*381 (Wire
uid 5114,0
shape (OrthoPolyLine
uid 5115,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "92750,80000,126250,101000"
pts [
"92750,101000"
"117000,101000"
"117000,80000"
"126250,80000"
]
)
start &219
end &89
sat 32
eat 32
sty 1
st 0
sf 1
tg (WTG
uid 5118,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5119,0
va (VaSet
)
xt "94000,100000,101700,101000"
st "config_data : (15:0)"
blo "94000,100800"
tm "WireNameMgr"
)
)
on &233
)
*382 (Wire
uid 5122,0
shape (OrthoPolyLine
uid 5123,0
va (VaSet
vasetType 3
)
xt "92750,82000,126250,104000"
pts [
"126250,82000"
"119000,82000"
"119000,104000"
"92750,104000"
]
)
start &91
end &221
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5126,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5127,0
va (VaSet
)
xt "121000,81000,126300,82000"
st "config_wr_en"
blo "121000,81800"
tm "WireNameMgr"
)
)
on &234
)
*383 (Wire
uid 5130,0
shape (OrthoPolyLine
uid 5131,0
va (VaSet
vasetType 3
)
xt "92750,83000,126250,105000"
pts [
"126250,83000"
"120000,83000"
"120000,105000"
"92750,105000"
]
)
start &93
end &223
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5134,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5135,0
va (VaSet
)
xt "121000,82000,126200,83000"
st "config_rd_en"
blo "121000,82800"
tm "WireNameMgr"
)
)
on &235
)
*384 (Wire
uid 5138,0
optionalChildren [
*385 (BdJunction
uid 5400,0
ps "OnConnectorStrategy"
shape (Circle
uid 5401,0
va (VaSet
vasetType 1
)
xt "57600,84600,58400,85400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 5139,0
va (VaSet
vasetType 3
)
xt "40750,80000,73250,102000"
pts [
"73250,102000"
"58000,102000"
"58000,80000"
"40750,80000"
]
)
start &220
end &35
ss 0
es 0
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5142,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5143,0
va (VaSet
)
xt "42000,79000,45400,80000"
st "roi_array"
blo "42000,79800"
tm "WireNameMgr"
)
)
on &148
)
*386 (Wire
uid 5146,0
shape (OrthoPolyLine
uid 5147,0
va (VaSet
vasetType 3
)
xt "37750,109000,73250,109000"
pts [
"73250,109000"
"37750,109000"
]
)
start &222
end &258
es 0
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5150,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5151,0
va (VaSet
)
xt "39000,108000,42700,109000"
st "dac_array"
blo "39000,108800"
tm "WireNameMgr"
)
)
on &236
)
*387 (Wire
uid 5168,0
shape (OrthoPolyLine
uid 5169,0
va (VaSet
vasetType 3
)
xt "58000,85000,71250,85000"
pts [
"58000,85000"
"71250,85000"
]
)
start &385
end &125
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5172,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5173,0
va (VaSet
)
xt "68000,84000,71400,85000"
st "roi_array"
blo "68000,84800"
tm "WireNameMgr"
)
)
on &148
)
*388 (Wire
uid 5184,0
shape (OrthoPolyLine
uid 5185,0
va (VaSet
vasetType 3
)
xt "40750,81000,73250,103000"
pts [
"73250,103000"
"57000,103000"
"57000,81000"
"40750,81000"
]
)
start &224
end &47
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5186,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5187,0
va (VaSet
)
xt "66000,102000,72200,103000"
st "config_start_cm"
blo "66000,102800"
tm "WireNameMgr"
)
)
on &237
)
*389 (Wire
uid 5190,0
shape (OrthoPolyLine
uid 5191,0
va (VaSet
vasetType 3
)
xt "40750,83000,73250,105000"
pts [
"73250,105000"
"55000,105000"
"55000,83000"
"40750,83000"
]
)
start &225
end &46
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5192,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5193,0
va (VaSet
)
xt "66000,104000,72500,105000"
st "config_ready_cm"
blo "66000,104800"
tm "WireNameMgr"
)
)
on &238
)
*390 (Wire
uid 5222,0
shape (OrthoPolyLine
uid 5223,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "148750,71000,153000,71000"
pts [
"148750,71000"
"153000,71000"
]
)
start &85
end &19
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5224,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5225,0
va (VaSet
isHidden 1
)
xt "150750,70000,152150,71000"
st "led"
blo "150750,70800"
tm "WireNameMgr"
)
)
on &239
)
*391 (Wire
uid 5281,0
shape (OrthoPolyLine
uid 5282,0
va (VaSet
vasetType 3
)
xt "40750,53000,126250,59000"
pts [
"126250,59000"
"73000,59000"
"73000,53000"
"40750,53000"
]
)
start &86
end &48
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5283,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5284,0
va (VaSet
)
xt "121250,58000,124850,59000"
st "s_trigger"
blo "121250,58800"
tm "WireNameMgr"
)
)
on &240
)
*392 (Wire
uid 5404,0
shape (OrthoPolyLine
uid 5405,0
va (VaSet
vasetType 3
)
xt "37750,85000,48000,107000"
pts [
"37750,107000"
"48000,107000"
"48000,85000"
"40750,85000"
]
)
start &259
end &50
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5406,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5407,0
va (VaSet
)
xt "39000,106000,45500,107000"
st "config_ready_spi"
blo "39000,106800"
tm "WireNameMgr"
)
)
on &243
)
*393 (Wire
uid 5474,0
shape (OrthoPolyLine
uid 5475,0
va (VaSet
vasetType 3
)
xt "37750,90000,44000,101000"
pts [
"37750,101000"
"44000,101000"
"44000,90000"
"40750,90000"
]
)
start &262
end &52
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5477,0
va (VaSet
)
xt "39750,100000,45050,101000"
st "sensor_ready"
blo "39750,100800"
tm "WireNameMgr"
)
)
on &241
)
*394 (Wire
uid 5480,0
shape (OrthoPolyLine
uid 5481,0
va (VaSet
vasetType 3
)
xt "37750,89000,45000,102000"
pts [
"37750,102000"
"45000,102000"
"45000,89000"
"40750,89000"
]
)
start &261
end &51
sat 32
eat 32
st 0
sf 1
tg (WTG
uid 5482,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5483,0
va (VaSet
)
xt "39750,101000,44950,102000"
st "sensor_array"
blo "39750,101800"
tm "WireNameMgr"
)
)
on &242
)
*395 (Wire
uid 5582,0
shape (OrthoPolyLine
uid 5583,0
va (VaSet
vasetType 3
lineColor "0,0,65535"
)
xt "69000,100000,73250,100000"
pts [
"69000,100000"
"73250,100000"
]
)
end &215
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 5586,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5587,0
va (VaSet
)
xt "70000,99000,73100,100000"
st "CLK_50"
blo "70000,99800"
tm "WireNameMgr"
)
)
on &164
)
*396 (Wire
uid 5602,0
optionalChildren [
&375
*397 (BdJunction
uid 6086,0
ps "OnConnectorStrategy"
shape (Circle
uid 6087,0
va (VaSet
vasetType 1
)
xt "67600,43600,68400,44400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 5603,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "15000,38000,76250,48000"
pts [
"18250,48000"
"15000,48000"
"15000,38000"
"68000,38000"
"68000,44000"
"76250,44000"
]
)
start &23
end &310
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5604,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5605,0
va (VaSet
)
xt "15000,47000,18100,48000"
st "CLK_25"
blo "15000,47800"
tm "WireNameMgr"
)
)
on &173
)
*398 (Wire
uid 5626,0
shape (OrthoPolyLine
uid 5627,0
va (VaSet
vasetType 3
)
xt "750,76000,18250,76000"
pts [
"18250,76000"
"750,76000"
]
)
start &45
end &248
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5630,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5631,0
va (VaSet
)
xt "11250,75000,18350,76000"
st "adc_data_array_int"
blo "11250,75800"
tm "WireNameMgr"
)
)
on &245
)
*399 (Wire
uid 5634,0
shape (OrthoPolyLine
uid 5635,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "750,77000,18250,77000"
pts [
"18250,77000"
"750,77000"
]
)
start &38
end &249
sat 32
eat 32
sty 1
st 0
sf 1
si 0
tg (WTG
uid 5638,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5639,0
va (VaSet
)
xt "11250,76000,16750,77000"
st "adc_otr : (3:0)"
blo "11250,76800"
tm "WireNameMgr"
)
)
on &244
)
*400 (Wire
uid 5646,0
shape (OrthoPolyLine
uid 5647,0
va (VaSet
vasetType 3
lineColor "49152,0,0"
)
xt "-26000,74000,-18750,74000"
pts [
"-26000,74000"
"-18750,74000"
]
)
end &251
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5652,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5653,0
va (VaSet
)
xt "-25000,74000,-20500,75000"
st "CLK_25_PS"
blo "-25000,74800"
tm "WireNameMgr"
)
)
on &162
)
*401 (Wire
uid 5745,0
shape (OrthoPolyLine
uid 5746,0
va (VaSet
vasetType 3
)
xt "37750,87000,46000,105000"
pts [
"40750,87000"
"46000,87000"
"46000,105000"
"37750,105000"
]
)
start &54
end &260
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5749,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5750,0
va (VaSet
)
xt "39000,104000,45200,105000"
st "config_start_spi"
blo "39000,104800"
tm "WireNameMgr"
)
)
on &255
)
*402 (Wire
uid 5805,0
shape (OrthoPolyLine
uid 5806,0
va (VaSet
vasetType 3
)
xt "16000,101000,20250,101000"
pts [
"16000,101000"
"20250,101000"
]
)
end &265
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 5809,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5810,0
va (VaSet
)
xt "17000,100000,20100,101000"
st "CLK_50"
blo "17000,100800"
tm "WireNameMgr"
)
)
on &164
)
*403 (Wire
uid 5813,0
shape (OrthoPolyLine
uid 5814,0
va (VaSet
vasetType 3
)
xt "12000,107000,20250,107000"
pts [
"20250,107000"
"12000,107000"
]
)
start &257
end &276
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5817,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5818,0
va (VaSet
isHidden 1
)
xt "13000,106000,14700,107000"
st "sclk"
blo "13000,106800"
tm "WireNameMgr"
)
)
on &272
)
*404 (Wire
uid 5821,0
shape (OrthoPolyLine
uid 5822,0
va (VaSet
vasetType 3
)
xt "12000,108000,20250,108000"
pts [
"20250,108000"
"12000,108000"
]
)
start &268
end &277
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5825,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5826,0
va (VaSet
isHidden 1
)
xt "13000,107000,14400,108000"
st "sio"
blo "13000,107800"
tm "WireNameMgr"
)
)
on &273
)
*405 (Wire
uid 5829,0
shape (OrthoPolyLine
uid 5830,0
va (VaSet
vasetType 3
)
xt "12000,105000,20250,105000"
pts [
"20250,105000"
"12000,105000"
]
)
start &263
end &278
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5833,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5834,0
va (VaSet
isHidden 1
)
xt "13000,104000,15800,105000"
st "dac_cs"
blo "13000,104800"
tm "WireNameMgr"
)
)
on &274
)
*406 (Wire
uid 5837,0
shape (OrthoPolyLine
uid 5838,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "12000,104000,20250,104000"
pts [
"20250,104000"
"12000,104000"
]
)
start &264
end &279
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 5841,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5842,0
va (VaSet
isHidden 1
)
xt "13000,103000,16900,104000"
st "sensor_cs"
blo "13000,103800"
tm "WireNameMgr"
)
)
on &275
)
*407 (Wire
uid 5950,0
shape (OrthoPolyLine
uid 5951,0
va (VaSet
vasetType 3
)
xt "40750,54000,126250,60000"
pts [
"126250,60000"
"72000,60000"
"72000,54000"
"40750,54000"
]
)
start &92
end &56
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5952,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5953,0
va (VaSet
)
xt "120250,59000,124850,60000"
st "new_config"
blo "120250,59800"
tm "WireNameMgr"
)
)
on &280
)
*408 (Wire
uid 5962,0
shape (OrthoPolyLine
uid 5963,0
va (VaSet
vasetType 3
)
xt "40750,55000,126250,61000"
pts [
"126250,61000"
"71000,61000"
"71000,55000"
"40750,55000"
]
)
start &90
end &55
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 5964,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5965,0
va (VaSet
)
xt "119250,60000,124850,61000"
st "config_started"
blo "119250,60800"
tm "WireNameMgr"
)
)
on &281
)
*409 (Wire
uid 6002,0
shape (OrthoPolyLine
uid 6003,0
va (VaSet
vasetType 3
)
xt "40750,82000,73250,104000"
pts [
"73250,104000"
"56000,104000"
"56000,82000"
"40750,82000"
]
)
start &226
end &57
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6004,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6005,0
va (VaSet
)
xt "66250,103000,73050,104000"
st "config_started_cu"
blo "66250,103800"
tm "WireNameMgr"
)
)
on &283
)
*410 (Wire
uid 6008,0
shape (OrthoPolyLine
uid 6009,0
va (VaSet
vasetType 3
)
xt "37750,86000,47000,106000"
pts [
"37750,106000"
"47000,106000"
"47000,86000"
"40750,86000"
]
)
start &266
end &59
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6010,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6011,0
va (VaSet
)
xt "39000,105000,46000,106000"
st "config_started_spi"
blo "39000,105800"
tm "WireNameMgr"
)
)
on &282
)
*411 (Wire
uid 6018,0
shape (OrthoPolyLine
uid 6019,0
va (VaSet
vasetType 3
)
xt "40750,71000,71250,76000"
pts [
"40750,71000"
"63000,71000"
"63000,76000"
"71250,76000"
]
)
start &58
end &127
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6020,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6021,0
va (VaSet
)
xt "41000,70000,48200,71000"
st "config_started_mm"
blo "41000,70800"
tm "WireNameMgr"
)
)
on &284
)
*412 (Wire
uid 6064,0
shape (OrthoPolyLine
uid 6065,0
va (VaSet
vasetType 3
)
xt "40750,79000,47000,79000"
pts [
"47000,79000"
"40750,79000"
]
)
end &60
sat 16
eat 32
st 0
sf 1
si 0
tg (WTG
uid 6068,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6069,0
va (VaSet
)
xt "42000,78000,45700,79000"
st "dac_array"
blo "42000,78800"
tm "WireNameMgr"
)
)
on &236
)
*413 (Wire
uid 6072,0
shape (OrthoPolyLine
uid 6073,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "-1250,21000,15000,38000"
pts [
"-1250,21000"
"15000,21000"
"15000,38000"
]
)
start &167
end &374
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6074,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6075,0
va (VaSet
)
xt "750,20000,3850,21000"
st "CLK_25"
blo "750,20800"
tm "WireNameMgr"
)
)
on &173
)
*414 (Wire
uid 6082,0
shape (OrthoPolyLine
uid 6083,0
va (VaSet
vasetType 3
lineColor "0,32896,0"
)
xt "68000,44000,71250,68000"
pts [
"71250,68000"
"68000,68000"
"68000,44000"
]
)
start &112
end &397
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6084,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6085,0
va (VaSet
)
xt "68000,67000,71100,68000"
st "CLK_25"
blo "68000,67800"
tm "WireNameMgr"
)
)
on &173
)
*415 (Wire
uid 6160,0
shape (OrthoPolyLine
uid 6161,0
va (VaSet
vasetType 3
)
xt "12000,109000,20250,109000"
pts [
"20250,109000"
"12000,109000"
]
)
start &267
end &286
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6164,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6165,0
va (VaSet
isHidden 1
)
xt "13000,108000,15000,109000"
st "mosi"
blo "13000,108800"
tm "WireNameMgr"
)
)
on &285
)
*416 (Wire
uid 6276,0
shape (OrthoPolyLine
uid 6277,0
va (VaSet
vasetType 3
)
xt "-23000,63000,-18750,63000"
pts [
"-23000,63000"
"-18750,63000"
]
)
end &104
sat 16
eat 32
st 0
sf 1
tg (WTG
uid 6280,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6281,0
va (VaSet
)
xt "-22000,62000,-17500,63000"
st "CLK_25_PS"
blo "-22000,62800"
tm "WireNameMgr"
)
)
on &162
)
*417 (Wire
uid 6362,0
shape (OrthoPolyLine
uid 6363,0
va (VaSet
vasetType 3
)
xt "148750,75000,153000,75000"
pts [
"148750,75000"
"153000,75000"
]
)
start &94
end &288
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6366,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6367,0
va (VaSet
isHidden 1
)
xt "150000,74000,153000,75000"
st "denable"
blo "150000,74800"
tm "WireNameMgr"
)
)
on &287
)
*418 (Wire
uid 6452,0
shape (OrthoPolyLine
uid 6453,0
va (VaSet
vasetType 3
)
xt "148750,76000,153000,76000"
pts [
"148750,76000"
"153000,76000"
]
)
start &95
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 6456,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6457,0
va (VaSet
isHidden 1
)
xt "150000,75000,155400,76000"
st "dwrite_enable"
blo "150000,75800"
tm "WireNameMgr"
)
)
on &289
)
*419 (Wire
uid 6540,0
shape (OrthoPolyLine
uid 6541,0
va (VaSet
vasetType 3
)
xt "7000,59000,18250,59000"
pts [
"7000,59000"
"182