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Last change
on this file since 228 was 228, checked in by dneise, 15 years ago |
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upload of first unstable release version
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File size:
1.1 KB
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| 1 | [ModelSim]
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| 2 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
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| 3 | simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
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| 4 | unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
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| 5 | unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
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| 6 | XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
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| 7 | [QuestaSim]
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| 8 | simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
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| 9 | unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
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| 10 | unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
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| 11 | XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
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| 12 | [XilinxISE]
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| 13 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
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| 14 | [hdl]
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| 15 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
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| 16 | unisim = $HDS_PROJECT_DIR/unisim/hdl
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| 17 | [hds]
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| 18 | FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds
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| 19 | unisim = $HDS_PROJECT_DIR/unisim/hds
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| 20 | [hds_settings]
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| 21 | default_library = FACT_FAD_lib
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| 22 | design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd
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| 23 | project_description = FPGA design for data acquisition from FACT
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| 24 | version = 1
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| 25 | [library_files_inclusion]
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| 26 | FACT_FAD_lib = specify
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| 27 | [library_type]
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| 28 | FACT_FAD_lib = regular
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| 29 | simprim = downstream_only
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| 30 | unimacro = downstream_only
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| 31 | unisim = standard
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| 32 | XilinxCoreLib = downstream_only
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| 33 | [shared]
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| 34 | others = $HDS_TEAM_HOME/shared.hdp
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