[ModelSim]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/work
simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
[QuestaSim]
simprim = C:/FPGAdv82PS/Xilinx_Lib/simprim
unimacro = C:/FPGAdv82PS/Xilinx_Lib/unimacro
unisim = C:/FPGAdv82PS/Xilinx_Lib/unisim
XilinxCoreLib = C:/FPGAdv82PS/Xilinx_Lib/XilinxCoreLib
[XilinxISE]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/ise
[hdl]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hdl
unisim = $HDS_PROJECT_DIR/unisim/hdl
[hds]
FACT_FAD_lib = $HDS_PROJECT_DIR/FACT_FAD_lib/hds
unisim = $HDS_PROJECT_DIR/unisim/hds
[hds_settings]
default_library = FACT_FAD_lib
design_root = FACT_FAD_lib.FAD_Board(struct)@f@a@d_@board/struct.bd
project_description = FPGA design for data acquisition from FACT
version = 1
[library_files_inclusion]
FACT_FAD_lib = specify
[library_type]
FACT_FAD_lib = regular
simprim = downstream_only
unimacro = downstream_only
unisim = standard
XilinxCoreLib = downstream_only
[shared]
others = $HDS_TEAM_HOME/shared.hdp