source: FPGA/FAD/unstable/FACT_FAD/FACT_FAD_lib/hdl/w5300_modul.vhd@ 251

Last change on this file since 251 was 228, checked in by dneise, 15 years ago
upload of first unstable release version
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1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date: 11:48:48 11/10/2009
6-- Design Name:
7-- Module Name: w5300_modul - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library FACT_FAD_lib;
25use FACT_FAD_lib.fad_definitions.ALL;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY w5300_modul IS
33 generic(
34 RAM_ADDR_WIDTH : integer := 14
35 );
36 PORT(
37 clk : IN std_logic;
38 wiz_reset : OUT std_logic := '1';
39 addr : OUT std_logic_vector (9 DOWNTO 0);
40 data : INOUT std_logic_vector (15 DOWNTO 0);
41 cs : OUT std_logic := '1';
42 wr : OUT std_logic := '1';
43 led : OUT std_logic_vector (7 DOWNTO 0) := (OTHERS => '0');
44 rd : OUT std_logic := '1';
45 int : IN std_logic;
46 write_length : IN std_logic_vector (16 DOWNTO 0);
47 ram_start_addr : IN std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
48 ram_data : IN std_logic_vector (15 DOWNTO 0);
49 ram_addr : OUT std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
50 data_valid : IN std_logic;
51 busy : OUT std_logic := '1';
52 write_header_flag, write_end_flag : IN std_logic;
53 fifo_channels : IN std_logic_vector (3 downto 0);
54 s_trigger : OUT std_logic := '0';
55 new_config : OUT std_logic := '0';
56 config_started : in std_logic;
57 config_addr : out std_logic_vector (7 downto 0);
58 config_data : inout std_logic_vector (15 downto 0) := (others => 'Z');
59 config_wr_en : out std_logic := '0';
60 config_rd_en : out std_logic := '0';
61 config_busy : in std_logic;
62
63 denable : out std_logic := '0'; -- default domino wave off
64 dwrite_enable : out std_logic := '0' -- default DWRITE low.
65 );
66
67-- Declarations
68
69END w5300_modul ;
70
71architecture Behavioral of w5300_modul is
72
73type state_init_type is (INTERRUPT, RESET, WRITE_REG, READ_REG, WRITE_DATA,
74 INIT, IM, MT, STX, STX1, STX2, STX3, SRX, SRX1, SRX2, SRX3, MAC, MAC1, MAC2, GW, GW1, SNM, SNM1, IP, IP1,
75 SI, SI1, SI2, SI3, SI4, SI5, SI6, ESTABLISH, EST1, CONFIG, MAIN, CHK_RECEIVED, READ_DATA);
76type state_write_type is (WR_START, WR_LENGTH, WR_WAIT1, WR_01, WR_02, WR_03, WR_04, WR_05, WR_06, WR_07, WR_08, WR_FIFO, WR_FIFO1, WR_ADC, WR_ADC1, WR_ADC2,
77 WR_ENDFLAG, WR_ENDFLAG1, WR_ENDFLAG2, WR_ENDFLAG3);
78type state_interrupt_1_type is (IR1_01, IR1_02, IR1_03, IR1_04);
79type state_interrupt_2_type is (IR2_01, IR2_02, IR2_03, IR2_04, IR2_05, IR2_06);
80type state_read_data_type is (RD_1, RD_2, RD_3, RD_4, RD_5, RD_6, RD_WAIT, RD_WAIT1, RD_END);
81
82signal RST_TIME : std_logic_vector(19 downto 0) := X"7A120";
83
84signal par_addr : std_logic_vector (9 downto 0) := (OTHERS => '0');
85signal par_data : std_logic_vector (15 downto 0) := (OTHERS => '0');
86signal data_read : std_logic_vector (15 downto 0) := (OTHERS => '0');
87signal adc_data_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
88
89signal state_init, next_state , next_state_tmp : state_init_type := RESET;
90signal count : std_logic_vector (2 downto 0) := "000";
91signal state_write : state_write_type := WR_START;
92signal state_interrupt_1 : state_interrupt_1_type := IR1_01;
93signal state_interrupt_2 : state_interrupt_2_type := IR2_01;
94signal state_read_data : state_read_data_type := RD_1;
95
96signal interrupt_ignore : std_logic := '1';
97signal int_flag : std_logic := '0';
98signal ram_access : std_logic := '0';
99
100signal zaehler : std_logic_vector (19 downto 0) := (OTHERS => '0');
101signal data_cnt : integer := 0;
102signal drs_cnt : integer :=0;
103signal channel_cnt : integer range 0 to 9 :=0;
104signal socket_cnt : std_logic_vector (2 downto 0) := "000";
105signal roi_max : std_logic_vector (10 downto 0);
106signal data_end : integer := 0;
107
108signal socket_tx_free : std_logic_vector (31 downto 0) := (others => '0');
109signal write_length_bytes : std_logic_vector (16 downto 0);
110
111signal socket_rx_received : std_logic_vector (31 downto 0) := (others => '0');
112signal chk_recv_cntr : integer range 0 to 10000 := 0;
113signal rx_packets_cnt : std_logic_vector (15 downto 0);
114signal next_packet_data : std_logic := '0';
115signal new_config_flag : std_logic := '0';
116
117signal trigger_stop : std_logic := '1';
118
119signal local_write_length : std_logic_vector (16 DOWNTO 0);
120signal local_ram_start_addr : std_logic_vector (RAM_ADDR_WIDTH-1 DOWNTO 0);
121signal local_ram_addr : std_logic_vector (RAM_ADDR_WIDTH-1 downto 0);
122signal local_socket_nr : std_logic_vector (2 DOWNTO 0);
123signal local_write_header_flag, local_write_end_flag : std_logic;
124signal local_fifo_channels : std_logic_vector (3 downto 0);
125
126begin
127
128 --synthesis translate_off
129 RST_TIME <= X"00120";
130 --synthesis translate_on
131
132 w5300_init_proc : process (clk, int)
133 begin
134
135 if rising_edge (clk) then
136
137 -- Interrupt low
138 if (int = '0') and (interrupt_ignore = '0') then
139 case state_interrupt_1 is
140 when IR1_01 =>
141 int_flag <= '1';
142 busy <= '1';
143 state_interrupt_1 <= IR1_02;
144 when IR1_02 =>
145 state_interrupt_1 <= IR1_03;
146 when IR1_03 =>
147 state_init <= INTERRUPT;
148 socket_cnt <= "000";
149 ram_access <= '0';
150 zaehler <= X"00000";
151 count <= "000";
152 int_flag <= '0';
153 interrupt_ignore <= '1';
154 state_interrupt_1 <= IR1_04;
155 when others =>
156 null;
157 end case;
158 end if; -- int = '0'
159
160 if int_flag = '0' then
161 case state_init is
162 -- Interrupt
163 when INTERRUPT =>
164 case state_interrupt_2 is
165 when IR2_01 =>
166 par_addr <= W5300_IR;
167 state_init <= READ_REG;
168 next_state <= INTERRUPT;
169 state_interrupt_2 <= IR2_02;
170 when IR2_02 =>
171 if (data_read (conv_integer(socket_cnt)) = '1') then -- Sx Interrupt
172 state_interrupt_2 <= IR2_03;
173 else
174 socket_cnt <= socket_cnt + 1;
175 if (socket_cnt = 7) then
176 state_interrupt_2 <= IR2_06;
177 else
178 state_interrupt_2 <= IR2_02;
179 end if;
180 end if;
181 when IR2_03 =>
182 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC; -- Sx Interrupt Register
183 state_init <= READ_REG;
184 next_state <= INTERRUPT;
185 state_interrupt_2 <= IR2_04;
186 when IR2_04 =>
187 par_addr <= W5300_S0_IR + socket_cnt * W5300_S_INC;
188 par_data <= data_read; -- clear Interrupts
189 state_init <= WRITE_REG;
190 next_state <= INTERRUPT;
191 state_interrupt_2 <= IR2_05;
192 when IR2_05 =>
193 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
194 par_data <= X"0010"; -- CLOSE
195 state_init <= WRITE_REG;
196 next_state <= INTERRUPT;
197 socket_cnt <= socket_cnt + 1;
198 if (socket_cnt = 7) then
199 state_interrupt_2 <= IR2_06;
200 else
201 state_interrupt_2 <= IR2_01;
202 end if;
203
204 when IR2_06 =>
205 state_interrupt_1 <= IR1_01;
206 state_interrupt_2 <= IR2_01;
207 socket_cnt <= "000";
208 state_init <= RESET;
209 end case;
210
211 -- reset W5300
212 when RESET =>
213 zaehler <= zaehler + 1;
214 wiz_reset <= '0';
215 led <= X"FF";
216 if (zaehler >= X"00064") then -- wait 2µs
217 wiz_reset <= '1';
218 end if;
219 if (zaehler = RST_TIME) then -- wait 10ms
220 zaehler <= X"00000";
221 socket_cnt <= "000";
222 count <= "000";
223 ram_access <= '0';
224 interrupt_ignore <= '0';
225 rd <= '1';
226 wr <= '1';
227 cs <= '1';
228 state_write <= WR_START;
229 state_init <= INIT;
230 end if;
231
232 -- Init
233 when INIT =>
234 par_addr <= W5300_MR;
235 par_data <= X"0000";
236 state_init <= WRITE_REG;
237 next_state <= IM;
238
239 -- Interrupt Mask
240 when IM =>
241 par_addr <= W5300_IMR;
242 par_data <= X"00FF"; -- S0-S7 Interrupts
243 state_init <= WRITE_REG;
244 next_state <= MT;
245
246 -- Memory Type
247 when MT =>
248 par_addr <= W5300_MTYPER;
249 par_data <= X"7FFF"; -- 8K RX, 120K TX-Buffer
250 state_init <= WRITE_REG;
251 next_state <= STX;
252
253 -- Socket TX Memory Size
254 when STX =>
255 par_data <= X"0F0F"; -- 15K TX
256
257 par_addr <= W5300_TMS01R;
258 state_init <=WRITE_REG;
259 next_state <= STX1;
260 when STX1 =>
261 par_addr <= W5300_TMS23R;
262 state_init <=WRITE_REG;
263 next_state <= STX2;
264 when STX2 =>
265 par_addr <= W5300_TMS45R;
266 state_init <=WRITE_REG;
267 next_state <= STX3;
268 when STX3 =>
269 par_addr <= W5300_TMS67R;
270 state_init <=WRITE_REG;
271 next_state <= SRX;
272
273 -- Socket RX Memory Size
274 when SRX =>
275 par_data <= X"0101"; -- 1K RX
276
277 par_addr <= W5300_RMS01R;
278 state_init <=WRITE_REG;
279 next_state <= SRX1;
280 when SRX1 =>
281 par_addr <= W5300_RMS23R;
282 state_init <=WRITE_REG;
283 next_state <= SRX2;
284 when SRX2 =>
285 par_addr <= W5300_RMS45R;
286 state_init <=WRITE_REG;
287 next_state <= SRX3;
288 when SRX3 =>
289 par_addr <= W5300_RMS67R;
290 state_init <=WRITE_REG;
291 next_state <= MAC;
292
293 -- MAC
294 when MAC =>
295 par_addr <= W5300_SHAR;
296 par_data <= MAC_ADDRESS (0);
297 state_init <= WRITE_REG;
298 next_state <= MAC1;
299 when MAC1 =>
300 par_addr <= W5300_SHAR + 2;
301 par_data <= MAC_ADDRESS (1);
302 state_init <= WRITE_REG;
303 next_state <= MAC2;
304 when MAC2 =>
305 par_addr <= W5300_SHAR + 4;
306 par_data <= MAC_ADDRESS (2);
307 state_init <= WRITE_REG;
308 next_state <= GW;
309
310 -- Gateway
311 when GW =>
312 par_addr <= W5300_GAR;
313 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (0),8);
314 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (1),8);
315 state_init <= WRITE_REG;
316 next_state <= GW1;
317 when GW1 =>
318 par_addr <= W5300_GAR + 2;
319 par_data (15 downto 8) <= conv_std_logic_vector(GATEWAY (2),8);
320 par_data (7 downto 0) <= conv_std_logic_vector(GATEWAY (3),8);
321 state_init <= WRITE_REG;
322 next_state <= SNM;
323
324 -- Subnet Mask
325 when SNM =>
326 par_addr <= W5300_SUBR;
327 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (0),8);
328 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (1),8);
329 state_init <= WRITE_REG;
330 next_state <= SNM1;
331 when SNM1 =>
332 par_addr <= W5300_SUBR + 2;
333 par_data (15 downto 8) <= conv_std_logic_vector(NETMASK (2),8);
334 par_data (7 downto 0) <= conv_std_logic_vector(NETMASK (3),8);
335 state_init <= WRITE_REG;
336 next_state <= IP;
337 -- Own IP-Address
338 when IP =>
339 par_addr <= W5300_SIPR;
340 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (0),8);
341 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (1),8);
342 state_init <= WRITE_REG;
343 next_state <= IP1;
344 when IP1 =>
345 par_addr <= W5300_SIPR + 2;
346 par_data (15 downto 8) <= conv_std_logic_vector(IP_ADDRESS (2),8);
347 par_data (7 downto 0) <= conv_std_logic_vector(IP_ADDRESS (3),8);
348 state_init <= WRITE_REG;
349 next_state <= SI;
350
351 -- Socket Init
352 when SI =>
353 par_addr <= W5300_S0_MR + socket_cnt * W5300_S_INC;
354 par_data <= X"0101"; -- ALIGN, TCP
355 state_init <= WRITE_REG;
356 next_state <= SI1;
357 -- Sx Interrupt Mask
358 when SI1 =>
359 par_addr <= W5300_S0_IMR + socket_cnt * W5300_S_INC;
360 par_data <= X"000A"; -- TIMEOUT, DISCON
361 state_init <= WRITE_REG;
362 next_state <= SI2;
363 when SI2 =>
364 par_addr <= W5300_S0_PORTR + socket_cnt * W5300_S_INC;
365 par_data <= conv_std_logic_vector(FIRST_PORT + unsigned (socket_cnt), 16);
366 state_init <= WRITE_REG;
367 next_state <= SI3;
368 when SI3 =>
369 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
370 par_data <= X"0001"; -- OPEN
371 state_init <= WRITE_REG;
372 next_state <= SI4;
373 when SI4 =>
374 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
375 state_init <= READ_REG;
376 next_state <= SI5;
377 when SI5 =>
378 if (data_read (7 downto 0) = X"13") then -- is open?
379 state_init <= SI6;
380 else
381 state_init <= SI4;
382 end if;
383 when SI6 =>
384 par_addr <= W5300_S0_CR + socket_cnt * W5300_S_INC;
385 par_data <= X"0002"; -- LISTEN
386 state_init <= WRITE_REG;
387 socket_cnt <= socket_cnt + 1;
388 if (socket_cnt = 7) then
389 socket_cnt <= "000";
390 next_state <= ESTABLISH; -- All Sockets open
391 else
392 next_state <= SI; -- Next Socket
393 end if;
394 -- End Socket Init
395
396 when ESTABLISH =>
397 par_addr <= W5300_S0_SSR + socket_cnt * W5300_S_INC;
398 state_init <= READ_REG;
399 next_state <= EST1;
400 when EST1 =>
401 led <= data_read (7 downto 0);
402 case data_read (7 downto 0) is
403 when X"17" => -- established
404 if (socket_cnt = 7) then
405 socket_cnt <= "000";
406 busy <= '0';
407 state_init <= MAIN;
408 else
409 socket_cnt <= socket_cnt + 1;
410 state_init <= ESTABLISH;
411 end if;
412 when others =>
413 state_init <= ESTABLISH;
414 end case;
415
416 when CONFIG =>
417 led <= X"F0";
418 new_config <= '1';
419 if (config_started = '1') then
420 led <= X"0F";
421 new_config <= '0';
422 busy <= '0';
423 state_init <= MAIN;
424 end if;
425
426 -- main "loop"
427 when MAIN =>
428 if (trigger_stop = '1') then
429 s_trigger <= '0';
430 end if;
431 if (chk_recv_cntr = 1000) then
432 chk_recv_cntr <= 0;
433 state_read_data <= RD_1;
434 state_init <= READ_DATA;
435 busy <= '1';
436 else
437 chk_recv_cntr <= chk_recv_cntr + 1;
438 if (data_valid = '1') then
439 local_write_length <= write_length;
440 local_ram_start_addr <= ram_start_addr;
441 local_ram_addr <= (others => '0');
442 local_write_header_flag <= write_header_flag;
443 local_write_end_flag <= write_end_flag;
444 local_fifo_channels <= fifo_channels;
445 next_state <= MAIN;
446 state_init <= WRITE_DATA;
447 busy <= '1';
448 end if;
449 end if;
450
451 -- read data from socket 0
452 when READ_DATA =>
453 case state_read_data is
454 when RD_1 =>
455 par_addr <= W5300_S0_RX_RSR;
456 state_init <= READ_REG;
457 next_state <= READ_DATA;
458 state_read_data <= RD_2;
459 when RD_2 =>
460 socket_rx_received (31 downto 16) <= data_read;
461 par_addr <= W5300_S0_RX_RSR + X"2";
462 state_init <= READ_REG;
463 next_state <= READ_DATA;
464 state_read_data <= RD_3;
465 when RD_3 =>
466 socket_rx_received (15 downto 0) <= data_read;
467 state_read_data <= RD_4;
468 when RD_4 =>
469 if (socket_rx_received (16 downto 0) > ('0' & X"000")) then
470 rx_packets_cnt <= socket_rx_received (16 downto 1); -- socket_rx_received / 2
471 state_read_data <= RD_5;
472 else
473 busy <= '0';
474 state_init <= MAIN;
475 end if;
476 when RD_5 =>
477 if (rx_packets_cnt > 0) then
478 rx_packets_cnt <= rx_packets_cnt - '1';
479 par_addr <= W5300_S0_RX_FIFOR;
480 state_init <= READ_REG;
481 next_state <= READ_DATA;
482 state_read_data <= RD_6;
483 else
484 state_read_data <= RD_END;
485-- if (new_config_flag = '1') then
486-- new_config_flag <= '0';
487-- state_init <= CONFIG;
488-- else
489-- busy <= '0';
490-- state_init <= MAIN;
491-- end if;
492 end if;
493 when RD_6 =>
494 led <= data_read (15 downto 8);
495 -- read command
496 if (next_packet_data = '0') then
497 case data_read (15 downto 8) is
498 when CMD_TRIGGER =>
499 trigger_stop <= '1';
500 s_trigger <= '1';
501 state_read_data <= RD_WAIT;
502 when CMD_DWRITE_RUN =>
503 dwrite_enable <= '1';
504 state_read_data <= RD_WAIT;
505 when CMD_DWRITE_STOP =>
506 dwrite_enable <= '0';
507 state_read_data <= RD_WAIT;
508 when CMD_DENABLE =>
509 denable <= '1';
510 state_read_data <= RD_WAIT;
511 when CMD_DDISABLE =>
512 denable <= '0';
513 state_read_data <= RD_WAIT;
514 when CMD_TRIGGER_C =>
515 trigger_stop <= '0';
516 s_trigger <= '1';
517 state_read_data <= RD_WAIT;
518 when CMD_TRIGGER_S =>
519 trigger_stop <= '1';
520 state_read_data <= RD_WAIT;
521 when CMD_WRITE =>
522 next_packet_data <= '1';
523 config_addr <= data_read (7 downto 0);
524 state_read_data <= RD_5;
525 when others =>
526 state_read_data <= RD_5;
527 end case;
528 -- read data
529 else
530 if (config_busy = '0') then
531 config_data <= data_read;
532 config_wr_en <= '1';
533 new_config_flag <= '1';
534 next_packet_data <= '0';
535 state_read_data <= RD_WAIT;
536 end if;
537 end if;
538 when RD_WAIT =>
539 state_read_data <= RD_WAIT1;
540 when RD_WAIT1 =>
541 config_data <= (others => 'Z');
542 config_wr_en <= '0';
543 state_read_data <= RD_5;
544 when RD_END =>
545 par_addr <= W5300_S0_CR;
546 par_data <= X"0040"; -- RECV
547 state_init <= WRITE_REG;
548 if (new_config_flag = '1') then
549 new_config_flag <= '0';
550 next_state <= CONFIG;
551 else
552 busy <= '0';
553 next_state <= MAIN;
554 end if;
555
556 end case; -- state_data_read
557
558
559
560 when WRITE_DATA =>
561 case state_write is
562 when WR_START =>
563 if (local_write_header_flag = '1') then
564 ram_addr <= local_ram_start_addr + 5; -- Address of Trigger-ID (15 downto 0) ????
565 end if;
566 state_write <= WR_WAIT1;
567 when WR_WAIT1 =>
568 state_write <= WR_LENGTH;
569 when WR_LENGTH =>
570 if (local_write_header_flag = '1') then
571 local_socket_nr <= ram_data (2 downto 0);
572 end if;
573 next_state_tmp <= next_state;
574 write_length_bytes <= local_write_length (15 downto 0) & '0'; -- shift left (*2)
575 data_cnt <= 0;
576 state_write <= WR_01;
577 -- Check FIFO Size
578 when WR_01 =>
579 par_addr <= W5300_S0_TX_FSR + local_socket_nr * W5300_S_INC;
580 state_init <= READ_REG;
581 next_state <= WRITE_DATA;
582 state_write <= WR_02;
583 when WR_02 =>
584 socket_tx_free (31 downto 16) <= data_read;
585 par_addr <= W5300_S0_TX_FSR + (local_socket_nr * W5300_S_INC) + X"2";
586 state_init <= READ_REG;
587 next_state <= WRITE_DATA;
588 state_write <= WR_03;
589 when WR_03 =>
590 socket_tx_free (15 downto 0) <= data_read;
591 state_write <= WR_04;
592 when WR_04 =>
593 if (socket_tx_free (16 downto 0) < write_length_bytes) then
594 state_write <= WR_01;
595 else
596 if (local_write_header_flag = '1') then
597 state_write <= WR_FIFO;
598 else
599 state_write <= WR_ADC;
600 end if;
601 end if;
602
603 -- Fill FIFO
604
605 -- Write Header
606 when WR_FIFO =>
607 ram_addr <= local_ram_start_addr + local_ram_addr;
608 state_write <= WR_FIFO1;
609 when WR_FIFO1 =>
610 data_cnt <= data_cnt + 1;
611 if (data_cnt < PACKAGE_HEADER_LENGTH) then --???
612 local_ram_addr <= local_ram_addr + 1;
613 if (data_cnt = 2 or data_cnt = 5 or data_cnt = 8 ) then -- skip empty words
614 local_ram_addr <= local_ram_addr + 2;
615 end if;
616 if (data_cnt = 9) then -- skip empty words
617 local_ram_addr <= local_ram_addr + 4;
618 end if;
619 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
620 ram_access <= '1';
621 state_init <= WRITE_REG;
622 next_state <= WRITE_DATA;
623 state_write <= WR_FIFO;
624 else
625 state_write <= WR_ADC;
626 end if;
627 -- End Write Header
628
629 -- Write ADC-Data
630 ---- Start...
631 when WR_ADC =>
632 adc_data_addr <= local_ram_start_addr + local_ram_addr;
633 drs_cnt <= 0;
634 channel_cnt <= 1;
635 data_cnt <= 0;
636 roi_max <= (others => '0');
637 data_end <= 3;
638 state_write <= WR_ADC1;
639
640 ---- Write Channel
641 when WR_ADC1 =>
642 -- read ROI and set end of Channel-Data
643 if (data_cnt = 3) then
644 data_end <= conv_integer (ram_data) + 3;
645 if (ram_data > roi_max) then
646 roi_max <= ram_data (10 downto 0);
647 end if;
648 end if;
649 ram_addr <= adc_data_addr + drs_cnt + (data_cnt * 4);
650 state_write <= WR_ADC2;
651 when WR_ADC2 =>
652 if (data_cnt < data_end) then
653 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
654 ram_access <= '1';
655 state_init <= WRITE_REG;
656 next_state <= WRITE_DATA;
657 data_cnt <= data_cnt + 1;
658 state_write <= WR_ADC1;
659 else
660 -- Next DRS
661 if (drs_cnt < 3) then
662 drs_cnt <= drs_cnt + 1;
663 data_cnt <= 0;
664 data_end <= 3;
665 state_write <= WR_ADC1;
666 else
667 -- Next Channel
668 if (channel_cnt < local_fifo_channels) then
669 channel_cnt <= channel_cnt + 1;
670 roi_max <= (others => '0');
671 drs_cnt <= 0;
672 data_cnt <= 0;
673 data_end <= 3;
674 adc_data_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
675 state_write <= WR_ADC1;
676 else
677 -- Ready
678 if (local_write_end_flag = '1') then
679 state_write <= WR_ENDFLAG;
680 else
681 state_write <= WR_05;
682 end if;
683 end if;
684 end if;
685 end if;
686 -- End Write ADC-Data
687
688 -- Write End Package Flag
689 when WR_ENDFLAG =>
690 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4);
691 state_write <= WR_ENDFLAG1;
692 when WR_ENDFLAG1 =>
693 par_addr <= W5300_S0_TX_FIFOR + local_socket_nr * W5300_S_INC;
694 ram_access <= '1';
695 state_init <= WRITE_REG;
696 next_state <= WRITE_DATA;
697 state_write <= WR_ENDFLAG2;
698 when WR_ENDFLAG2 =>
699 ram_addr <= adc_data_addr + ((conv_integer(roi_max) + 3) * 4) + 1;
700 state_write <= WR_ENDFLAG3;
701 when WR_ENDFLAG3 =>
702 state_init <= WRITE_REG;
703 next_state <= WRITE_DATA;
704 state_write <= WR_05;
705
706 -- End Write End Package Flag
707
708 --Send FIFO
709 when WR_05 =>
710 ram_access <= '0';
711 par_addr <= W5300_S0_TX_WRSR + local_socket_nr * W5300_S_INC;
712 par_data <= (0 => write_length_bytes (16), others => '0');
713 state_init <= WRITE_REG;
714 state_write <= WR_06;
715 when WR_06 =>
716 par_addr <= W5300_S0_TX_WRSR + (local_socket_nr * W5300_S_INC) + X"2";
717 par_data <= write_length_bytes (15 downto 0);
718 state_init <= WRITE_REG;
719 state_write <= WR_07;
720 when WR_07 =>
721 par_addr <= W5300_S0_CR + local_socket_nr * W5300_S_INC;
722 par_data <= X"0020"; -- Send
723 state_init <= WRITE_REG;
724 state_write <= WR_08;
725 when others =>
726 busy <= '0';
727 state_init <= next_state_tmp;
728 state_write <= WR_START;
729 end case;
730 -- End WRITE_DATA
731
732 when READ_REG =>
733 case count is
734 when "000" =>
735 cs <= '0';
736 rd <= '0';
737 wr <= '1';
738 data <= (others => 'Z'); -- !!!!!!!!!!
739 count <= "001";
740 addr <= par_addr;
741 when "001" =>
742 count <= "010";
743 when "010" =>
744 count <= "100";
745 when "100" =>
746 data_read <= data;
747 count <= "110";
748 when "110" =>
749 count <= "111";
750 when "111" =>
751 cs <= '1';
752 rd <= '1';
753 count <= "000";
754 state_init <= next_state;
755 when others =>
756 null;
757 end case;
758
759 when WRITE_REG =>
760 case count is
761 when "000" =>
762 cs <= '0';
763 wr <= '0';
764 rd <= '1';
765 addr <= par_addr;
766 if (ram_access = '1') then
767 data <= ram_data;
768 else
769 data <= par_data;
770 end if;
771 count <= "100";
772 when "100" =>
773 count <= "101";
774 when "101" =>
775 count <= "110";
776 when "110" =>
777 cs <= '1';
778 wr <= '1';
779 state_init <= next_state;
780 count <= "000";
781 when others =>
782 null;
783 end case;
784
785 when others =>
786 null;
787 end case;
788 end if; -- int_flag = '0'
789
790 end if; -- rising_edge (clk)
791
792 end process w5300_init_proc;
793
794end Behavioral;
795
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