source: FPGA/FTU/FTU_control.vhd @ 9828

Last change on this file since 9828 was 9828, checked in by weitzel, 10 years ago
FTU_control entity added
File size: 3.4 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:        ETH Zurich, Institute for Particle Physics
3-- Engineer:       P. Vogler, Q. Weitzel
4--
5-- Create Date:    08/06/2010
6-- Design Name:   
7-- Module Name:    FTU_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:    Control FSM of FACT FTU board                                                                               
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26library ftu_definitions;
27USE ftu_definitions.ftu_array_types.all;
28
29---- Uncomment the following library declaration if instantiating
30---- any Xilinx primitives in this code.
31--library UNISIM;
32--use UNISIM.VComponents.all;
33
34entity FTU_control is
35  port(
36    clk_50MHz    : IN  std_logic;
37    clk_ready    : IN  std_logic;
38    config_ready : IN std_logic;
39    reset        : OUT std_logic;
40    config_start : OUT std_logic
41  );
42end FTU_control;
43
44architecture Behavioral of FTU_control is
45
46  signal reset_sig : STD_LOGIC := '0';
47
48  signal config_start_sig : STD_LOGIC := '0';
49  signal config_ready_sig : STD_LOGIC := '0';
50 
51  type FTU_control_StateType is (IDLE, INIT, RUNNING, RESET_ALL);
52  signal FTU_control_State, FTU_control_NextState: FTU_control_StateType;
53 
54begin
55   
56  --FTU control state machine (two-process implementation)
57
58  FTU_control_Registers: process (clk_50MHz)
59  begin
60    if Rising_edge(clk_50MHz) then
61      FTU_control_State <= FTU_control_NextState;
62    end if;
63  end process FTU_control_Registers;
64
65  FTU_control_C_logic: process (FTU_control_State, clk_ready, config_ready_sig)
66  begin
67    FTU_control_NextState <= FTU_control_State;
68    case FTU_control_State is
69      when IDLE =>                      -- wait for DMCs to lock
70        reset_sig <= '0';
71        config_start_sig <= '0';
72        --ram_web_sig <= "0";
73        if (clk_ready = '1') then
74          FTU_control_NextState <= RUNNING;
75        end if;         
76      when INIT =>                      -- load default config data to RAM
77        reset_sig <= '0';
78        config_start_sig <= '0';
79        --ram_web_sig <= "1";
80        --ram_adb_cntr <= ram_adb_cntr + 1;
81        --ram_adb_sig <= conv_std_logic_vector(ram_adb_cntr, 4);       
82        --if (ram_adb_cntr < 4) then
83        --  ram_dib_sig <= DEFAULT_ENABLE(ram_adb_cntr);
84        --  FTU_top_NextState <= INIT;
85        --elsif (ram_adb_cntr < 4 + 5) then
86        --  ram_dib_sig <= conv_std_logic_vector(DEFAULT_DAC(ram_adb_cntr - 4), 16);
87        --  FTU_top_NextState <= INIT;
88        --elsif (ram_adb_cntr < 32) then
89        --  ram_dib_sig <= (others => '0');
90        --  FTU_top_NextState <= INIT;
91        --else
92        --  ram_adb_cntr <= 0;
93        --  ram_web_sig <= "0";
94        --  FTU_top_NextState <= RUNNING;
95        --end if;
96      when RUNNING =>                   -- count triggers and react to commands
97        reset_sig <= '0';
98        config_start_sig <= '0';
99        --ram_web_sig <= "0";
100      when RESET_ALL =>                     -- reset/clear and start from scratch
101        reset_sig <= '1';
102        config_start_sig <= '0';
103        --ram_web_sig <= "0";
104        FTU_control_NextState <= IDLE;
105    end case;
106  end process FTU_control_C_logic;
107
108  reset <= reset_sig;
109 
110end Behavioral;
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