source: FPGA/FTU/FTU_dac_control.vhd@ 156

Last change on this file since 156 was 156, checked in by qweitzel, 11 years ago
First check-in of VHDL code for FTU: counters, dcm, spi
File size: 5.6 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 16:24:08 01/19/2010
6-- Design Name:
7-- Module Name: FTU_dac_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: control DAC on FTU board to set trigger thresholds
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25---- Uncomment the following library declaration if instantiating
26---- any Xilinx primitives in this code.
27--library UNISIM;
28--use UNISIM.VComponents.all;
29
30entity FTU_dac_control is
31 port(
32 clk : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
34 miso : IN STD_LOGIC;
35 clr : OUT STD_LOGIC;
36 mosi : OUT STD_LOGIC;
37 sck : OUT STD_LOGIC;
38 cs_ld : OUT STD_LOGIC
39 );
40end FTU_dac_control;
41
42architecture Behavioral of FTU_dac_control is
43
44 constant RESET_ACTIVE : std_logic := '0';
45
46 component spi_interface_16
47 port(
48 clk : IN STD_LOGIC;
49 clkdiv : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
50 cpha : IN STD_LOGIC;
51 cpol : IN STD_LOGIC;
52 miso : IN STD_LOGIC;
53 rcv_cpol : IN STD_LOGIC;
54 rcv_full_reset : IN STD_LOGIC;
55 reset : IN STD_LOGIC;
56 ss_in_n : IN STD_LOGIC;
57 ss_mask_reg : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
58 start : IN STD_LOGIC;
59 xmit_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
60 xmit_empty_reset : IN STD_LOGIC;
61 rcv_load : INOUT STD_LOGIC;
62 sck : INOUT STD_LOGIC;
63 ss_in_int : INOUT STD_LOGIC;
64 ss_n_int : INOUT STD_LOGIC;
65 xmit_empty : INOUT STD_LOGIC;
66 done : OUT STD_LOGIC;
67 mosi : OUT STD_LOGIC;
68 rcv_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
69 rcv_full : OUT STD_LOGIC;
70 ss_n : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
71 );
72 end component;
73
74 component upcnt16
75 port(
76 full : out STD_LOGIC;
77 clr : in STD_LOGIC;
78 reset : in STD_Logic;
79 clk : in STD_LOGIC
80 );
81 end component;
82
83 signal clk_sig : std_logic;
84 signal done_sig : std_logic;
85 signal start_sig : std_logic;
86 signal slave_select_sig : std_logic;
87 signal full_sig : std_logic;
88 signal clr_wcnt_sig : std_logic;
89 signal s_clock_sig : std_logic;
90 signal D_sig : STD_LOGIC_VECTOR (15 DOWNTO 0);
91 signal ss_n_sig : STD_LOGIC_VECTOR (7 DOWNTO 0);
92 signal reset_sig : STD_LOGIC;
93 signal reset_sig_inv : STD_LOGIC;
94
95 -- Build an enumerated type for the state machine
96 type state_type is (Idle);
97
98 -- Register to hold the current state
99 signal state, next_state: state_type;
100
101begin
102
103 reset_sig <= reset;
104 reset_sig_inv <= not(reset);
105 clk_sig <= clk;
106 sck <= s_clock_sig;
107 clr <= reset_sig_inv;
108 cs_ld <= ss_n_sig(0);
109
110 -- FSM for dac control: first process
111 FSM_Registers: process(clk_sig, reset_sig)
112 begin
113 if reset_sig = '1' then
114 state <= Idle;
115 elsif Rising_edge(clk_sig) then
116 state <= next_state;
117 end if;
118 end process;
119
120 -- FSM for dac control: second process
121 FSM_logic: process(state)
122 begin
123 next_state <= state;
124 case state is
125 when Idle =>
126 D_sig <= "0001000100000000";
127 start_sig <= '0';
128 slave_select_sig <= '0';
129 clr_wcnt_sig <= '0';
130 end case;
131 end process;
132
133 Inst_spi_interface_16 : spi_interface_16
134 port map(
135 clk=>clk_sig, clkdiv(1)=>'0', clkdiv(0)=>'0',
136 cpha=>'1', cpol=>'1', miso=>'1', rcv_cpol=>'1',
137 rcv_full_reset=>not(RESET_ACTIVE), reset=>reset_sig_inv, ss_in_n=>'1',
138 ss_mask_reg(7)=>'0', ss_mask_reg(6)=>'0',
139 ss_mask_reg(5)=>'0', ss_mask_reg(4)=>'0',
140 ss_mask_reg(3)=>'0', ss_mask_reg(2)=>'0',
141 ss_mask_reg(1)=>'0', ss_mask_reg(0)=>slave_select_sig,
142 start=>start_sig,
143 xmit_data(15)=>D_sig(15), xmit_data(14)=>D_sig(14),
144 xmit_data(13)=>D_sig(13), xmit_data(12)=>D_sig(12),
145 xmit_data(11)=>D_sig(11), xmit_data(10)=>D_sig(10),
146 xmit_data(9)=>D_sig(9), xmit_data(8)=>D_sig(8),
147 xmit_data(7)=>D_sig(7), xmit_data(6)=>D_sig(6),
148 xmit_data(5)=>D_sig(5), xmit_data(4)=>D_sig(4),
149 xmit_data(3)=>D_sig(3), xmit_data(2)=>D_sig(2),
150 xmit_data(1)=>D_sig(1), xmit_data(0)=>D_sig(0),
151 xmit_empty_reset=>RESET_ACTIVE,
152 rcv_load=>open,
153 sck=>s_clock_sig,
154 ss_in_int=>open,
155 ss_n_int=>open,
156 xmit_empty=>open,
157 done=>done_sig, mosi=>mosi,rcv_data=>open,
158 --rcv_data(15)=>open, rcv_data(14)=>open,
159 --rcv_data(13)=>open, rcv_data(12)=>open,
160 --rcv_data(11)=>open, rcv_data(10)=>open,
161 --rcv_data(9)=>open, rcv_data(8)=>open,
162 --rcv_data(7)=>open, rcv_data(6)=>open,
163 --rcv_data(5)=>open, rcv_data(4)=>open,
164 --rcv_data(3)=>open, rcv_data(2)=>open,
165 --rcv_data(1)=>open, rcv_data(0)=>open,
166 rcv_full=>open,ss_n=>ss_n_sig
167 --ss_n(7)=>open, ss_n(6)=>open, ss_n(5)=>open, ss_n(4)=>open,
168 --ss_n(3)=>open, ss_n(2)=>open, ss_n(1)=>open, ss_n(0)=>cs_ld
169 );
170
171 wait_cnt: upcnt16
172 port map(
173 full => full_sig,
174 clr => clr_wcnt_sig,
175 reset => reset_sig,
176 clk => clk_sig
177 );
178
179end Behavioral;
180
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