----------------------------------------------------------------------------------
-- Company:        ETH Zurich, Institute for Particle Physics
-- Engineer:       P. Vogler, Q. Weitzel
-- 
-- Create Date:    11:59:40 01/19/2010 
-- Design Name:    
-- Module Name:    FTU_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description:    Top level entity of FACT FTU board 										
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity FTU_top is
  port(
    -- global control 
    ext_clk   : IN  STD_LOGIC;                      -- external clock from FTU board
    brd_add   : IN  STD_LOGIC_VECTOR(5 downto 0);   -- global board address

    -- rate counters LVDS inputs
    -- use IBUFDS differential input buffer
    patch_A_p     : IN  STD_LOGIC;                  -- logic signal from first trigger patch
    patch_A_n     : IN  STD_LOGIC;           
    patch_B_p     : IN  STD_LOGIC;                  -- logic signal from second trigger patch
    patch_B_n     : IN  STD_LOGIC;
    patch_C_p     : IN  STD_LOGIC;                  -- logic signal from third trigger patch
    patch_C_n     : IN  STD_LOGIC;
    patch_D_p     : IN  STD_LOGIC;                  -- logic signal from fourth trigger patch
    patch_D_n     : IN  STD_LOGIC;
    trig_prim_p   : IN  STD_LOGIC;                  -- logic signal from n-out-of-4 circuit
    trig_prim_n   : IN  STD_LOGIC;
    
    -- DAC interface
    sck           : OUT STD_LOGIC;                  -- serial clock to DAC
    mosi          : OUT STD_LOGIC;                  -- serial data to DAC, master-out-slave-in
    clr           : OUT STD_LOGIC;                  -- clear signal to DAC
    cs_ld         : OUT STD_LOGIC;                  -- chip select or load to DAC
    
    -- RS-485 interface to FTM
    rx            : IN  STD_LOGIC;                  -- serial data from FTM
    tx            : OUT STD_LOGIC;                  -- serial data to FTM
    rx_en         : OUT STD_LOGIC;                  -- enable RS-485 receiver
    tx_en         : OUT STD_LOGIC;                  -- enable RS-485 transmitter

    -- analog buffer enable
    enables_A   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
    enables_B   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
    enables_C   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs
    enables_D   : OUT STD_LOGIC_VECTOR(8 downto 0);  -- individual enables for analog inputs

    -- testpoints
    TP_A        : out STD_LOGIC_VECTOR(11 downto 0)   -- testpoints    
  );
end FTU_top;


architecture Behavioral of FTU_top is

  component FTU_dac_dcm
    port(
      CLKIN_IN        : IN  STD_LOGIC; 
      RST_IN          : IN  STD_LOGIC; 
      CLKFX_OUT       : OUT STD_LOGIC; 
      CLKIN_IBUFG_OUT : OUT STD_LOGIC; 
      LOCKED_OUT      : OUT STD_LOGIC
    );
  end component;
  
  component FTU_dac_control
    port(
      clk      : IN  STD_LOGIC;
      reset    : IN  STD_LOGIC;
      miso     : IN  STD_LOGIC;
      clr      : OUT STD_LOGIC;
      mosi     : OUT STD_LOGIC;
      sck      : OUT STD_LOGIC;
      cs_ld    : OUT STD_LOGIC
    );
  end component;

  signal reset_sig : STD_LOGIC := '0';  -- initialize reset to 0 at power up 
  signal clk_5M_sig : STD_LOGIC;

  type FTU_top_StateType is (Init, Running, Reset);
  signal FTU_top_State, FTU_top_NextState: FTU_top_StateType;
  
begin

  Inst_FTU_dac_dcm : FTU_dac_dcm
    port map(
      CLKIN_IN => ext_clk,
      RST_IN => reset_sig,
      CLKFX_OUT => clk_5M_sig,
      CLKIN_IBUFG_OUT => open,
      LOCKED_OUT => open
    );
  
  Inst_FTU_dac_control : FTU_dac_control
    port map(
      clk   => clk_5M_sig,
      reset => reset_sig,
      miso  => '0',
      clr   => clr,
      mosi  => mosi,
      sck   => sck,
      cs_ld => cs_ld      
    );

  --FTU main state machine (two-process implementation)

  FTU_top_Registers: process (ext_clk)
  begin
    if Rising_edge(ext_clk) then
      FTU_top_State <= FTU_top_NextState;
    end if;
  end process FTU_top_Registers;

  FTU_top_C_logic: process (FTU_top_State)
  begin
    FTU_top_NextState <= FTU_top_State;
    case FTU_top_State is
      when Init =>
        reset_sig <= '0';
        FTU_top_NextState <= Running;
      when Running =>
      when Reset =>
        reset_sig <= '1';
        FTU_top_NextState <= Init;
    end case;
  end process FTU_top_C_logic;
  
end Behavioral;

--What is missing?
--UART  
--registers (enables, DAC values etc.)
--rate counters
--main state machine for FTU: talks to DAC, reads counters, listens to UART