source: FPGA/FTU/FTU_top.vhd@ 155

Last change on this file since 155 was 155, checked in by qweitzel, 12 years ago
First check-in of FTU top entity VHDL code
File size: 3.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25---- Uncomment the following library declaration if instantiating
26---- any Xilinx primitives in this code.
27--library UNISIM;
28--use UNISIM.VComponents.all;
29
30entity FTU_top is
31 port(
32 ext_clk : IN STD_LOGIC; --external clock from FTU board
33 brd_add : IN STD_LOGIC_VECTOR(7 downto 0); --global board address
34 patch1 : IN STD_LOGIC; --logic signal from first trigger patch
35 patch2 : IN STD_LOGIC; --logic signal from second trigger patch
36 patch3 : IN STD_LOGIC; --logic signal from third trigger patch
37 patch4 : IN STD_LOGIC; --logic signal from fourth trigger patch
38 trig_prim : IN STD_LOGIC; --logic signal from n-out-of-4 circuit
39 miso : IN STD_LOGIC; --serial data from DAC
40 rx : IN STD_LOGIC; --serial data from FTM
41 enables : OUT STD_LOGIC_VECTOR(35 downto 0); --individual enables for analog inputs
42 clr : OUT STD_LOGIC; --clear signal to DAC
43 cs_ld : OUT STD_LOGIC; --chip select or load to DAC
44 sck : OUT STD_LOGIC; --serial clock to DAC
45 mosi : OUT STD_LOGIC; --serial data to DAC
46 tx : OUT STD_LOGIC --serial data to FTM
47 );
48end FTU_top;
49
50architecture Behavioral of FTU_top is
51
52 component FTU_dac_dcm
53 port(
54 CLKIN_IN : IN STD_LOGIC;
55 RST_IN : IN STD_LOGIC;
56 CLKFX_OUT : OUT STD_LOGIC;
57 CLKIN_IBUFG_OUT : OUT STD_LOGIC;
58 LOCKED_OUT : OUT STD_LOGIC
59 );
60 end component;
61
62 component FTU_dac_control
63 port(
64 clk : IN STD_LOGIC;
65 reset : IN STD_LOGIC;
66 miso : IN STD_LOGIC;
67 clr : OUT STD_LOGIC;
68 mosi : OUT STD_LOGIC;
69 sck : OUT STD_LOGIC;
70 cs_ld : OUT STD_LOGIC
71 );
72 end component;
73
74 signal clk_sig : STD_LOGIC;
75 signal reset_sig : STD_LOGIC;
76 signal miso_sig : STD_LOGIC;
77 signal clr_sig : STD_LOGIC;
78 signal mosi_sig : STD_LOGIC;
79 signal sck_sig : STD_LOGIC;
80 signal cs_ld_sig : STD_LOGIC;
81
82 signal clk_5M_sig : STD_LOGIC;
83
84begin
85
86 clk_sig <= ext_clk;
87 reset_sig <= '0';--where to get this from?
88 miso_sig <= miso;
89
90 clr <= clr_sig;
91 mosi <= mosi_sig;
92 sck <= sck_sig;
93 cs_ld <= cs_ld_sig;
94
95 Inst_FTU_dac_dcm : FTU_dac_dcm
96 port map(
97 CLKIN_IN => clk_sig,
98 RST_IN => reset_sig,
99 CLKFX_OUT => clk_5M_sig,
100 CLKIN_IBUFG_OUT => open,
101 LOCKED_OUT => open
102 );
103
104 Inst_FTU_dac_control : FTU_dac_control
105 port map(
106 clk => clk_5M_sig,
107 reset => reset_sig,
108 miso => miso_sig,
109 clr => clr_sig,
110 mosi => mosi_sig,
111 sck => sck_sig,
112 cs_ld => cs_ld_sig
113 );
114
115end Behavioral;
116
117--What is missing?
118--UART
119--registers (enables, DAC values etc.)
120--rate counters
121--main state machine for FTU: talks to DAC, reads counters, listens to UART
122
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