1 | ----------------------------------------------------------------------------------
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2 | -- Company: ETH Zurich, Institute for Particle Physics
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3 | -- Engineer: P. Vogler, Q. Weitzel
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4 | --
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5 | -- Create Date: 11:59:40 01/19/2010
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6 | -- Design Name:
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7 | -- Module Name: FTU_top - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description: Top level entity of FACT FTU board
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | library IEEE;
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21 | use IEEE.STD_LOGIC_1164.ALL;
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22 | use IEEE.STD_LOGIC_ARITH.ALL;
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23 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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24 |
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25 | ---- Uncomment the following library declaration if instantiating
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26 | ---- any Xilinx primitives in this code.
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27 | --library UNISIM;
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28 | --use UNISIM.VComponents.all;
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29 |
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30 | entity FTU_top is
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31 | port(
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32 | ext_clk : IN STD_LOGIC; --external clock from FTU board
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33 | brd_add : IN STD_LOGIC_VECTOR(7 downto 0); --global board address
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34 | patch1 : IN STD_LOGIC; --logic signal from first trigger patch
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35 | patch2 : IN STD_LOGIC; --logic signal from second trigger patch
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36 | patch3 : IN STD_LOGIC; --logic signal from third trigger patch
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37 | patch4 : IN STD_LOGIC; --logic signal from fourth trigger patch
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38 | trig_prim : IN STD_LOGIC; --logic signal from n-out-of-4 circuit
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39 | miso : IN STD_LOGIC; --serial data from DAC
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40 | rx : IN STD_LOGIC; --serial data from FTM
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41 | enables : OUT STD_LOGIC_VECTOR(35 downto 0); --individual enables for analog inputs
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42 | clr : OUT STD_LOGIC; --clear signal to DAC
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43 | cs_ld : OUT STD_LOGIC; --chip select or load to DAC
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44 | sck : OUT STD_LOGIC; --serial clock to DAC
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45 | mosi : OUT STD_LOGIC; --serial data to DAC
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46 | tx : OUT STD_LOGIC --serial data to FTM
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47 | );
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48 | end FTU_top;
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49 |
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50 | architecture Behavioral of FTU_top is
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51 |
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52 | component FTU_dac_dcm
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53 | port(
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54 | CLKIN_IN : IN STD_LOGIC;
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55 | RST_IN : IN STD_LOGIC;
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56 | CLKFX_OUT : OUT STD_LOGIC;
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57 | CLKIN_IBUFG_OUT : OUT STD_LOGIC;
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58 | LOCKED_OUT : OUT STD_LOGIC
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59 | );
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60 | end component;
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61 |
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62 | component FTU_dac_control
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63 | port(
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64 | clk : IN STD_LOGIC;
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65 | reset : IN STD_LOGIC;
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66 | miso : IN STD_LOGIC;
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67 | clr : OUT STD_LOGIC;
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68 | mosi : OUT STD_LOGIC;
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69 | sck : OUT STD_LOGIC;
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70 | cs_ld : OUT STD_LOGIC
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71 | );
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72 | end component;
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73 |
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74 | signal clk_sig : STD_LOGIC;
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75 | signal reset_sig : STD_LOGIC;
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76 | signal miso_sig : STD_LOGIC;
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77 | signal clr_sig : STD_LOGIC;
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78 | signal mosi_sig : STD_LOGIC;
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79 | signal sck_sig : STD_LOGIC;
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80 | signal cs_ld_sig : STD_LOGIC;
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81 |
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82 | signal clk_5M_sig : STD_LOGIC;
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83 |
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84 | begin
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85 |
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86 | clk_sig <= ext_clk;
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87 | reset_sig <= '0';--where to get this from?
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88 | miso_sig <= miso;
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89 |
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90 | clr <= clr_sig;
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91 | mosi <= mosi_sig;
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92 | sck <= sck_sig;
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93 | cs_ld <= cs_ld_sig;
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94 |
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95 | Inst_FTU_dac_dcm : FTU_dac_dcm
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96 | port map(
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97 | CLKIN_IN => clk_sig,
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98 | RST_IN => reset_sig,
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99 | CLKFX_OUT => clk_5M_sig,
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100 | CLKIN_IBUFG_OUT => open,
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101 | LOCKED_OUT => open
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102 | );
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103 |
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104 | Inst_FTU_dac_control : FTU_dac_control
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105 | port map(
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106 | clk => clk_5M_sig,
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107 | reset => reset_sig,
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108 | miso => miso_sig,
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109 | clr => clr_sig,
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110 | mosi => mosi_sig,
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111 | sck => sck_sig,
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112 | cs_ld => cs_ld_sig
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113 | );
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114 |
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115 | end Behavioral;
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116 |
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117 | --What is missing?
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118 | --UART
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119 | --registers (enables, DAC values etc.)
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120 | --rate counters
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121 | --main state machine for FTU: talks to DAC, reads counters, listens to UART
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122 |
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