source: FPGA/FTU/FTU_top.vhd@ 157

Last change on this file since 157 was 157, checked in by pavogler, 12 years ago
port list updated in FTU_top entity
File size: 4.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24
25---- Uncomment the following library declaration if instantiating
26---- any Xilinx primitives in this code.
27--library UNISIM;
28--use UNISIM.VComponents.all;
29
30
31
32entity FTU_top is
33 port(
34 -- global control
35 ext_clk : IN STD_LOGIC; -- external clock from FTU board
36 reset : in STD_LOGIC; -- reset
37 brd_add : IN STD_LOGIC_VECTOR(7 downto 0); -- global board address
38
39 -- rate counters LVDS inputs
40 -- use IBUFDS differential input buffer
41 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
42 patch_A_n : IN STD_LOGIC;
43 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
44 patch_B_n : IN STD_LOGIC;
45 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
46 patch_C_n : IN STD_LOGIC;
47 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
48 patch_D_n : IN STD_LOGIC;
49 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
50 trig_prim_n : IN STD_LOGIC;
51
52 -- DAC interface
53 -- miso : IN STD_LOGIC; -- master-in-slave-out
54 sck : OUT STD_LOGIC; -- serial clock to DAC
55 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
56 clr : OUT STD_LOGIC; -- clear signal to DAC
57 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
58
59 -- RS-485 interface to FTM
60 rx : IN STD_LOGIC; -- serial data from FTM
61 tx : OUT STD_LOGIC; -- serial data to FTM
62 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
63 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
64
65 -- analog buffer enable
66 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
67 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
68 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
69 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70
71 -- testpoints
72 TP_A : out STD_LOGIC_VECTOR(7 downto 0) -- testpoints
73 );
74end FTU_top;
75
76
77architecture Behavioral of FTU_top is
78
79 component FTU_dac_dcm
80 port(
81 CLKIN_IN : IN STD_LOGIC;
82 RST_IN : IN STD_LOGIC;
83 CLKFX_OUT : OUT STD_LOGIC;
84 CLKIN_IBUFG_OUT : OUT STD_LOGIC;
85 LOCKED_OUT : OUT STD_LOGIC
86 );
87 end component;
88
89 component FTU_dac_control
90 port(
91 clk : IN STD_LOGIC;
92 reset : IN STD_LOGIC;
93 miso : IN STD_LOGIC;
94 clr : OUT STD_LOGIC;
95 mosi : OUT STD_LOGIC;
96 sck : OUT STD_LOGIC;
97 cs_ld : OUT STD_LOGIC
98 );
99 end component;
100
101 signal clk_sig : STD_LOGIC;
102 signal reset_sig : STD_LOGIC;
103 signal miso_sig : STD_LOGIC;
104 signal clr_sig : STD_LOGIC;
105 signal mosi_sig : STD_LOGIC;
106 signal sck_sig : STD_LOGIC;
107 signal cs_ld_sig : STD_LOGIC;
108
109 signal clk_5M_sig : STD_LOGIC;
110
111begin
112
113 clk_sig <= ext_clk;
114 reset_sig <= '0';--where to get this from?
115 -- miso_sig <= miso;
116
117 clr <= clr_sig;
118 mosi <= mosi_sig;
119 sck <= sck_sig;
120 cs_ld <= cs_ld_sig;
121
122 Inst_FTU_dac_dcm : FTU_dac_dcm
123 port map(
124 CLKIN_IN => clk_sig,
125 RST_IN => reset_sig,
126 CLKFX_OUT => clk_5M_sig,
127 CLKIN_IBUFG_OUT => open,
128 LOCKED_OUT => open
129 );
130
131 Inst_FTU_dac_control : FTU_dac_control
132 port map(
133 clk => clk_5M_sig,
134 reset => reset_sig,
135 miso => miso_sig,
136 clr => clr_sig,
137 mosi => mosi_sig,
138 sck => sck_sig,
139 cs_ld => cs_ld_sig
140 );
141
142end Behavioral;
143
144--What is missing?
145--UART
146--registers (enables, DAC values etc.)
147--rate counters
148--main state machine for FTU: talks to DAC, reads counters, listens to UART
149
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