source: FPGA/FTU/FTU_top.vhd@ 251

Last change on this file since 251 was 251, checked in by qweitzel, 11 years ago
ucf file added to new design
File size: 4.0 KB
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1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 11:59:40 01/19/2010
6-- Design Name:
7-- Module Name: FTU_top - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Top level entity of FACT FTU board
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Revision 0.02 - New design of FTU firmware, 12.07.2010, Q. Weitzel
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26---- Uncomment the following library declaration if instantiating
27---- any Xilinx primitives in this code.
28--library UNISIM;
29--use UNISIM.VComponents.all;
30
31
32entity FTU_top is
33 port(
34 -- global control
35 ext_clk : IN STD_LOGIC; -- external clock from FTU board
36 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
37 brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
38
39 -- rate counters LVDS inputs
40 -- use IBUFDS differential input buffer
41 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
42 patch_A_n : IN STD_LOGIC;
43 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
44 patch_B_n : IN STD_LOGIC;
45 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
46 patch_C_n : IN STD_LOGIC;
47 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
48 patch_D_n : IN STD_LOGIC;
49 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
50 trig_prim_n : IN STD_LOGIC;
51
52 -- DAC interface
53 sck : OUT STD_LOGIC; -- serial clock to DAC
54 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
55 clr : OUT STD_LOGIC; -- clear signal to DAC
56 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
57
58 -- RS-485 interface to FTM
59 rx : IN STD_LOGIC; -- serial data from FTM
60 tx : OUT STD_LOGIC; -- serial data to FTM
61 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
62 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
63
64 -- analog buffer enable
65 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
66 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
67 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
68 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
69
70 -- testpoints
71 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
72 );
73end FTU_top;
74
75
76architecture Behavioral of FTU_top is
77
78 signal reset_sig : STD_LOGIC := '0'; -- initialize reset to 0 at power up
79 signal clk_5M_sig : STD_LOGIC;
80
81 type FTU_top_StateType is (Init, Running, Reset);
82 signal FTU_top_State, FTU_top_NextState: FTU_top_StateType;
83
84begin
85
86 --FTU main state machine (two-process implementation)
87
88 FTU_top_Registers: process (ext_clk)
89 begin
90 if Rising_edge(ext_clk) then
91 FTU_top_State <= FTU_top_NextState;
92 end if;
93 end process FTU_top_Registers;
94
95 FTU_top_C_logic: process (FTU_top_State)
96 begin
97 FTU_top_NextState <= FTU_top_State;
98 case FTU_top_State is
99 when Init =>
100 reset_sig <= '0';
101 FTU_top_NextState <= Running;
102 when Running =>
103 when Reset =>
104 reset_sig <= '1';
105 FTU_top_NextState <= Init;
106 end case;
107 end process FTU_top_C_logic;
108
109end Behavioral;
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