source: FPGA/FTU/FTU_top_tb.vhd@ 156

Last change on this file since 156 was 156, checked in by qweitzel, 11 years ago
First check-in of VHDL code for FTU: counters, dcm, spi
File size: 3.4 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 14:57:43 01/19/2010
6-- Design Name:
7-- Module Name: /home/qweitzel/FPGA/FACT/FTU/source/FTU_top_tb.vhd
8-- Project Name: FTUsim01
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for top level entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33entity FTU_top_tb is
34end FTU_top_tb;
35
36architecture behavior of FTU_top_tb is
37
38 -- Component Declaration for the Unit Under Test (UUT)
39
40 component FTU_top
41 port(
42 ext_clk : IN STD_LOGIC;
43 brd_add : IN STD_LOGIC_VECTOR(7 downto 0);
44 patch1 : IN STD_LOGIC;
45 patch2 : IN STD_LOGIC;
46 patch3 : IN STD_LOGIC;
47 patch4 : IN STD_LOGIC;
48 trig_prim : IN STD_LOGIC;
49 miso : IN STD_LOGIC;
50 rx : IN STD_LOGIC;
51 enables : OUT STD_LOGIC_VECTOR(35 downto 0);
52 clr : OUT STD_LOGIC;
53 cs_ld : OUT STD_LOGIC;
54 sck : OUT STD_LOGIC;
55 mosi : OUT STD_LOGIC;
56 tx : OUT STD_LOGIC
57 );
58 end component;
59
60 --Inputs
61 signal ext_clk : STD_LOGIC := '0';
62 signal brd_add : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
63 signal patch1 : STD_LOGIC := '0';
64 signal patch2 : STD_LOGIC := '0';
65 signal patch3 : STD_LOGIC := '0';
66 signal patch4 : STD_LOGIC := '0';
67 signal trig_prim : STD_LOGIC := '0';
68 signal miso : STD_LOGIC := '0';
69 signal rx : STD_LOGIC := '0';
70
71 --Outputs
72 signal enables : STD_LOGIC_VECTOR(35 downto 0);
73 signal clr : STD_LOGIC;
74 signal cs_ld : STD_LOGIC;
75 signal sck : STD_LOGIC;
76 signal mosi : STD_LOGIC;
77 signal tx : STD_LOGIC;
78
79 -- Clock period definitions
80 constant ext_clk_period : TIME := 20 ns;
81
82begin
83
84 -- Instantiate the Unit Under Test (UUT)
85 uut: FTU_top
86 port map(
87 ext_clk => ext_clk,
88 brd_add => brd_add,
89 patch1 => patch1,
90 patch2 => patch2,
91 patch3 => patch3,
92 patch4 => patch4,
93 trig_prim => trig_prim,
94 miso => miso,
95 rx => rx,
96 enables => enables,
97 clr => clr,
98 cs_ld => cs_ld,
99 sck => sck,
100 mosi => mosi,
101 tx => tx
102 );
103
104 -- Clock process definitions
105 ext_clk_proc: process
106 begin
107 ext_clk <= '0';
108 wait for ext_clk_period/2;
109 ext_clk <= '1';
110 wait for ext_clk_period/2;
111 end process ext_clk_proc;
112
113 -- Stimulus process
114 stim_proc: process
115 begin
116 -- hold reset state for 100ms.
117 wait for 100ms;
118
119 wait for ext_clk_period*10;
120
121 -- insert stimulus here
122
123 wait;
124 end process stim_proc;
125
126end;
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