source: FPGA/FTU/FTU_top_tb.vhd@ 158

Last change on this file since 158 was 158, checked in by qweitzel, 11 years ago
testbench adjusted to last FTU_top entity changes
File size: 6.0 KB
Line 
1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 14:57:43 01/19/2010
6-- Design Name:
7-- Module Name: /home/qweitzel/FPGA/FACT/FTU/source/FTU_top_tb.vhd
8-- Project Name: FTUsim01
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for top level entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33entity FTU_top_tb is
34end FTU_top_tb;
35
36architecture behavior of FTU_top_tb is
37
38 -- Component Declaration for the Unit Under Test (UUT)
39
40 component FTU_top
41 port(
42 -- global control
43 ext_clk : IN STD_LOGIC; -- external clock from FTU board
44 reset : in STD_LOGIC; -- reset
45 brd_add : IN STD_LOGIC_VECTOR(7 downto 0); -- global board address
46
47 -- rate counters LVDS inputs
48 -- use IBUFDS differential input buffer
49 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
50 patch_A_n : IN STD_LOGIC;
51 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
52 patch_B_n : IN STD_LOGIC;
53 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
54 patch_C_n : IN STD_LOGIC;
55 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
56 patch_D_n : IN STD_LOGIC;
57 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
58 trig_prim_n : IN STD_LOGIC;
59
60 -- DAC interface
61 -- miso : IN STD_LOGIC; -- master-in-slave-out
62 sck : OUT STD_LOGIC; -- serial clock to DAC
63 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
64 clr : OUT STD_LOGIC; -- clear signal to DAC
65 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
66
67 -- RS-485 interface to FTM
68 rx : IN STD_LOGIC; -- serial data from FTM
69 tx : OUT STD_LOGIC; -- serial data to FTM
70 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
71 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
72
73 -- analog buffer enable
74 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
75 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
76 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
77 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
78
79 -- testpoints
80 TP_A : out STD_LOGIC_VECTOR(7 downto 0) -- testpoints
81 );
82 end component;
83
84 --Inputs
85 signal ext_clk : STD_LOGIC := '0';
86 signal reset : STD_LOGIC := '0';
87 signal brd_add : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
88 signal patch_A_p : STD_LOGIC := '0';
89 signal patch_A_n : STD_LOGIC := '0';
90 signal patch_B_p : STD_LOGIC := '0';
91 signal patch_B_n : STD_LOGIC := '0';
92 signal patch_C_p : STD_LOGIC := '0';
93 signal patch_C_n : STD_LOGIC := '0';
94 signal patch_D_p : STD_LOGIC := '0';
95 signal patch_D_n : STD_LOGIC := '0';
96 signal trig_prim_p : STD_LOGIC := '0';
97 signal trig_prim_n : STD_LOGIC := '0';
98 -- signal miso : STD_LOGIC := '0';
99 signal rx : STD_LOGIC := '0';
100
101 --Outputs
102 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
103 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
104 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
105 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
106 signal clr : STD_LOGIC;
107 signal cs_ld : STD_LOGIC;
108 signal sck : STD_LOGIC;
109 signal mosi : STD_LOGIC;
110 signal tx : STD_LOGIC;
111 signal rx_en : STD_LOGIC;
112 signal tx_en : STD_LOGIC;
113 signal TP_A : STD_LOGIC_VECTOR(7 downto 0);
114
115 -- Clock period definitions
116 constant ext_clk_period : TIME := 20 ns;
117
118begin
119
120 -- Instantiate the Unit Under Test (UUT)
121 uut: FTU_top
122 port map(
123 ext_clk => ext_clk,
124 reset => reset,
125 brd_add => brd_add,
126 patch_A_p => patch_A_p,
127 patch_A_n => patch_A_n,
128 patch_B_p => patch_B_p,
129 patch_B_n => patch_B_n,
130 patch_C_p => patch_C_p,
131 patch_C_n => patch_C_n,
132 patch_D_p => patch_D_p,
133 patch_D_n => patch_D_n,
134 trig_prim_p => trig_prim_p,
135 trig_prim_n => trig_prim_n,
136 -- miso => miso,
137 rx => rx,
138 rx_en => rx_en,
139 enables_A => enables_A,
140 enables_B => enables_B,
141 enables_C => enables_C,
142 enables_D => enables_D,
143 clr => clr,
144 cs_ld => cs_ld,
145 sck => sck,
146 mosi => mosi,
147 tx => tx,
148 tx_en => tx_en,
149 TP_A => TP_A
150 );
151
152 -- Clock process definitions
153 ext_clk_proc: process
154 begin
155 ext_clk <= '0';
156 wait for ext_clk_period/2;
157 ext_clk <= '1';
158 wait for ext_clk_period/2;
159 end process ext_clk_proc;
160
161 -- Stimulus process
162 stim_proc: process
163 begin
164 -- hold reset state for 100ms.
165 wait for 100ms;
166
167 wait for ext_clk_period*10;
168
169 -- insert stimulus here
170
171 wait;
172 end process stim_proc;
173
174end;
Note: See TracBrowser for help on using the repository browser.