source: FPGA/FTU/FTU_top_tb.vhd@ 207

Last change on this file since 207 was 207, checked in by qweitzel, 11 years ago
updated FTU_top entity
File size: 5.7 KB
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1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 14:57:43 01/19/2010
6-- Design Name:
7-- Module Name: /home/qweitzel/FPGA/FACT/FTU/source/FTU_top_tb.vhd
8-- Project Name: FTUsim01
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for top level entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33entity FTU_top_tb is
34end FTU_top_tb;
35
36architecture behavior of FTU_top_tb is
37
38 -- Component Declaration for the Unit Under Test (UUT)
39
40 component FTU_top
41 port(
42 -- global control
43 ext_clk : IN STD_LOGIC; -- external clock from FTU board
44 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- global board address
45
46 -- rate counters LVDS inputs
47 -- use IBUFDS differential input buffer
48 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
49 patch_A_n : IN STD_LOGIC;
50 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
51 patch_B_n : IN STD_LOGIC;
52 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
53 patch_C_n : IN STD_LOGIC;
54 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
55 patch_D_n : IN STD_LOGIC;
56 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
57 trig_prim_n : IN STD_LOGIC;
58
59 -- DAC interface
60 sck : OUT STD_LOGIC; -- serial clock to DAC
61 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
62 clr : OUT STD_LOGIC; -- clear signal to DAC
63 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
64
65 -- RS-485 interface to FTM
66 rx : IN STD_LOGIC; -- serial data from FTM
67 tx : OUT STD_LOGIC; -- serial data to FTM
68 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
69 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
70
71 -- analog buffer enable
72 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
73 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
74 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
75 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
76
77 -- testpoints
78 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
79 );
80 end component;
81
82 --Inputs
83 signal ext_clk : STD_LOGIC := '0';
84 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
85 signal patch_A_p : STD_LOGIC := '0';
86 signal patch_A_n : STD_LOGIC := '0';
87 signal patch_B_p : STD_LOGIC := '0';
88 signal patch_B_n : STD_LOGIC := '0';
89 signal patch_C_p : STD_LOGIC := '0';
90 signal patch_C_n : STD_LOGIC := '0';
91 signal patch_D_p : STD_LOGIC := '0';
92 signal patch_D_n : STD_LOGIC := '0';
93 signal trig_prim_p : STD_LOGIC := '0';
94 signal trig_prim_n : STD_LOGIC := '0';
95 signal rx : STD_LOGIC := '0';
96
97 --Outputs
98 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
99 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
100 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
101 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
102 signal clr : STD_LOGIC;
103 signal cs_ld : STD_LOGIC;
104 signal sck : STD_LOGIC;
105 signal mosi : STD_LOGIC;
106 signal tx : STD_LOGIC;
107 signal rx_en : STD_LOGIC;
108 signal tx_en : STD_LOGIC;
109 signal TP_A : STD_LOGIC_VECTOR(11 downto 0);
110
111 -- Clock period definitions
112 constant ext_clk_period : TIME := 20 ns;
113
114begin
115
116 -- Instantiate the Unit Under Test (UUT)
117 uut: FTU_top
118 port map(
119 ext_clk => ext_clk,
120 brd_add => brd_add,
121 patch_A_p => patch_A_p,
122 patch_A_n => patch_A_n,
123 patch_B_p => patch_B_p,
124 patch_B_n => patch_B_n,
125 patch_C_p => patch_C_p,
126 patch_C_n => patch_C_n,
127 patch_D_p => patch_D_p,
128 patch_D_n => patch_D_n,
129 trig_prim_p => trig_prim_p,
130 trig_prim_n => trig_prim_n,
131 rx => rx,
132 rx_en => rx_en,
133 enables_A => enables_A,
134 enables_B => enables_B,
135 enables_C => enables_C,
136 enables_D => enables_D,
137 clr => clr,
138 cs_ld => cs_ld,
139 sck => sck,
140 mosi => mosi,
141 tx => tx,
142 tx_en => tx_en,
143 TP_A => TP_A
144 );
145
146 -- Clock process definitions
147 ext_clk_proc: process
148 begin
149 ext_clk <= '0';
150 wait for ext_clk_period/2;
151 ext_clk <= '1';
152 wait for ext_clk_period/2;
153 end process ext_clk_proc;
154
155 -- Stimulus process
156 stim_proc: process
157 begin
158 -- hold reset state for 100ms.
159 wait for 100ms;
160
161 wait for ext_clk_period*10;
162
163 -- insert stimulus here
164
165 wait;
166 end process stim_proc;
167
168end;
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