source: FPGA/FTU/FTU_top_tb.vhd@ 234

Last change on this file since 234 was 234, checked in by qweitzel, 11 years ago
ucf file for FTU updated
File size: 5.9 KB
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1--------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 14:57:43 01/19/2010
6-- Design Name:
7-- Module Name: /home/qweitzel/FPGA/FACT/FTU/source/FTU_top_tb.vhd
8-- Project Name: FTUsim01
9-- Target Device:
10-- Tool versions:
11-- Description: Testbench for top level entity of FACT FTU board
12--
13-- VHDL Test Bench Created by ISE for module: FTU_top
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28library IEEE;
29use IEEE.STD_LOGIC_1164.ALL;
30use IEEE.STD_LOGIC_UNSIGNED.ALL;
31use IEEE.NUMERIC_STD.ALL;
32
33entity FTU_top_tb is
34end FTU_top_tb;
35
36architecture behavior of FTU_top_tb is
37
38 -- Component Declaration for the Unit Under Test (UUT)
39
40 component FTU_top
41 port(
42 -- global control
43 ext_clk : IN STD_LOGIC; -- external clock from FTU board
44 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
45 brd_id : in STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
46
47 -- rate counters LVDS inputs
48 -- use IBUFDS differential input buffer
49 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
50 patch_A_n : IN STD_LOGIC;
51 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
52 patch_B_n : IN STD_LOGIC;
53 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
54 patch_C_n : IN STD_LOGIC;
55 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
56 patch_D_n : IN STD_LOGIC;
57 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
58 trig_prim_n : IN STD_LOGIC;
59
60 -- DAC interface
61 sck : OUT STD_LOGIC; -- serial clock to DAC
62 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
63 clr : OUT STD_LOGIC; -- clear signal to DAC
64 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
65
66 -- RS-485 interface to FTM
67 rx : IN STD_LOGIC; -- serial data from FTM
68 tx : OUT STD_LOGIC; -- serial data to FTM
69 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
70 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
71
72 -- analog buffer enable
73 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
74 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
75 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
76 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
77
78 -- testpoints
79 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
80 );
81 end component;
82
83 --Inputs
84 signal ext_clk : STD_LOGIC := '0';
85 signal brd_add : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
86 signal brd_id : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
87 signal patch_A_p : STD_LOGIC := '0';
88 signal patch_A_n : STD_LOGIC := '0';
89 signal patch_B_p : STD_LOGIC := '0';
90 signal patch_B_n : STD_LOGIC := '0';
91 signal patch_C_p : STD_LOGIC := '0';
92 signal patch_C_n : STD_LOGIC := '0';
93 signal patch_D_p : STD_LOGIC := '0';
94 signal patch_D_n : STD_LOGIC := '0';
95 signal trig_prim_p : STD_LOGIC := '0';
96 signal trig_prim_n : STD_LOGIC := '0';
97 signal rx : STD_LOGIC := '0';
98
99 --Outputs
100 signal enables_A : STD_LOGIC_VECTOR(8 downto 0);
101 signal enables_B : STD_LOGIC_VECTOR(8 downto 0);
102 signal enables_C : STD_LOGIC_VECTOR(8 downto 0);
103 signal enables_D : STD_LOGIC_VECTOR(8 downto 0);
104 signal clr : STD_LOGIC;
105 signal cs_ld : STD_LOGIC;
106 signal sck : STD_LOGIC;
107 signal mosi : STD_LOGIC;
108 signal tx : STD_LOGIC;
109 signal rx_en : STD_LOGIC;
110 signal tx_en : STD_LOGIC;
111 signal TP_A : STD_LOGIC_VECTOR(11 downto 0);
112
113 -- Clock period definitions
114 constant ext_clk_period : TIME := 20 ns;
115
116begin
117
118 -- Instantiate the Unit Under Test (UUT)
119 uut: FTU_top
120 port map(
121 ext_clk => ext_clk,
122 brd_add => brd_add,
123 brd_id => brd_id,
124 patch_A_p => patch_A_p,
125 patch_A_n => patch_A_n,
126 patch_B_p => patch_B_p,
127 patch_B_n => patch_B_n,
128 patch_C_p => patch_C_p,
129 patch_C_n => patch_C_n,
130 patch_D_p => patch_D_p,
131 patch_D_n => patch_D_n,
132 trig_prim_p => trig_prim_p,
133 trig_prim_n => trig_prim_n,
134 rx => rx,
135 rx_en => rx_en,
136 enables_A => enables_A,
137 enables_B => enables_B,
138 enables_C => enables_C,
139 enables_D => enables_D,
140 clr => clr,
141 cs_ld => cs_ld,
142 sck => sck,
143 mosi => mosi,
144 tx => tx,
145 tx_en => tx_en,
146 TP_A => TP_A
147 );
148
149 -- Clock process definitions
150 ext_clk_proc: process
151 begin
152 ext_clk <= '0';
153 wait for ext_clk_period/2;
154 ext_clk <= '1';
155 wait for ext_clk_period/2;
156 end process ext_clk_proc;
157
158 -- Stimulus process
159 stim_proc: process
160 begin
161 -- hold reset state for 100ms.
162 wait for 100ms;
163
164 wait for ext_clk_period*10;
165
166 -- insert stimulus here
167
168 wait;
169 end process stim_proc;
170
171end;
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