source: FPGA/FTU/dac_spi/FTU_spi_clock_gen.vhd@ 9526

Last change on this file since 9526 was 273, checked in by qweitzel, 14 years ago
new structure for FTU firmware, not yet finished
File size: 1.0 KB
Line 
1--
2-- VHDL Architecture FACT_FAD_lib.spi_clock_generator.beha
3--
4-- Created:
5-- by - Benjamin Krumm.UNKNOWN (EEPC8)
6-- at - 14:49:19 01.04.2010
7--
8-- using Mentor Graphics HDL Designer(TM) 2009.1 (Build 12)
9--
10-- adapted for FTU by Q. Weitzel
11
12LIBRARY ieee;
13USE ieee.std_logic_1164.all;
14USE ieee.std_logic_arith.all;
15USE ieee.std_logic_unsigned.all;
16
17ENTITY FTU_spi_clock_generator IS
18 GENERIC(
19 CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz
20 );
21 PORT(
22 clk : IN std_logic;
23 sclk : OUT std_logic := '0'
24 );
25END FTU_spi_clock_generator;
26
27ARCHITECTURE beha OF FTU_spi_clock_generator IS
28
29BEGIN
30
31 spi_clk_proc: process (clk)
32 variable Z: integer range 0 to clk_divider - 1;
33 begin
34 if rising_edge(clk) then
35 if (Z < clk_divider - 1) then
36 Z := Z + 1;
37 else
38 Z := 0;
39 end if;
40 if (Z = 0) then
41 sclk <= '1';
42 end if;
43 if (Z = clk_divider / 2) then
44 sclk <= '0';
45 end if;
46 end if;
47 end process spi_clk_proc;
48
49END ARCHITECTURE beha;
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