source: FPGA/FTU/dac_spi/FTU_spi_interface.vhd@ 2620

Last change on this file since 2620 was 273, checked in by qweitzel, 14 years ago
new structure for FTU firmware, not yet finished
File size: 3.7 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 07/01/2010
6-- Design Name:
7-- Module Name: FTU_spi_interface - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Based on VHDL Entity FACT_FAD_lib.spi_interface.symbol
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library ftu_definitions;
25USE ftu_definitions.ftu_array_types.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32ENTITY FTU_spi_interface IS
33 PORT(
34 clk_50MHz : IN std_logic;
35 config_start : IN std_logic;
36 dac_array : IN dac_array_type;
37 config_ready : OUT std_logic;
38 config_started : OUT std_logic := '0';
39 dac_cs : OUT std_logic;
40 mosi : OUT std_logic := '0';
41 sclk : OUT std_logic
42 );
43END FTU_spi_interface;
44
45ARCHITECTURE struct OF FTU_spi_interface IS
46
47 SIGNAL dac_config_ready : std_logic;
48 SIGNAL dac_config_start : std_logic;
49 SIGNAL dac_id : std_logic_vector(2 DOWNTO 0);
50 SIGNAL data : std_logic_vector(15 DOWNTO 0);
51 SIGNAL sclk_internal : std_logic;
52
53 COMPONENT FTU_spi_clock_generator
54 GENERIC (
55 CLK_DIVIDER : integer := 25 --2 MHz @ 50 MHz
56 );
57 PORT (
58 clk : IN std_logic;
59 sclk : OUT std_logic := '0'
60 );
61 END COMPONENT;
62
63 COMPONENT FTU_spi_controller
64 PORT (
65 clk : IN std_logic;
66 dac_id : IN std_logic_vector (2 DOWNTO 0);
67 dac_start : IN std_logic;
68 dac_cs : OUT std_logic := '1';
69 dac_ready : OUT std_logic := '0';
70 mosi : OUT std_logic := '0';
71 data : IN std_logic_vector (15 DOWNTO 0) := (others => '0')
72 );
73 END COMPONENT;
74
75 COMPONENT FTU_spi_distributor
76 PORT (
77 clk : IN std_logic;
78 config_start : IN std_logic;
79 dac_array : IN dac_array_type;
80 dac_config_ready : IN std_logic;
81 config_ready : OUT std_logic := '0';
82 config_started : OUT std_logic := '0';
83 dac_config_start : OUT std_logic := '0';
84 dac_id : OUT std_logic_vector (2 DOWNTO 0) := (others => '0');
85 data : OUT std_logic_vector (15 DOWNTO 0) := (others => '0')
86 );
87 END COMPONENT;
88
89BEGIN
90
91 Inst_FTU_spi_clock_generator : FTU_spi_clock_generator
92 GENERIC MAP(
93 CLK_DIVIDER => 25 --2 MHz @ 50 MHz
94 )
95 PORT MAP(
96 clk => clk_50MHz,
97 sclk => sclk_internal
98 );
99
100 Inst_FTU_spi_controller : FTU_spi_controller
101 PORT MAP (
102 clk => sclk_internal,
103 mosi => mosi,
104 dac_id => dac_id,
105 data => data,
106 dac_cs => dac_cs,
107 dac_start => dac_config_start,
108 dac_ready => dac_config_ready
109 );
110
111 Inst_FTU_spi_distributor : FTU_spi_distributor
112 PORT MAP (
113 clk => sclk_internal,
114 config_start => config_start,
115 config_ready => config_ready,
116 config_started => config_started,
117 dac_array => dac_array,
118 dac_config_start => dac_config_start,
119 dac_config_ready => dac_config_ready,
120 dac_id => dac_id,
121 data => data
122 );
123
124 sclk <= sclk_internal;
125
126END struct;
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