########################################################
# FTU Board 
# FACT Trigger Unit
#
# Pin location constraints
#
# by Patrick Vogler
########################################################


#Clock
#######################################################
NET Clk LOC = Y11 | IOSTANDARD=LVCMOS33;		


# RS-485 Interface
#######################################################
NET 485_RE LOC  = T20 | IOSTANDARD=LVCMOS33;		
NET 485_DE LOC  = U20 | IOSTANDARD=LVCMOS33;		
NET 485_DO LOC  = U19 | IOSTANDARD=LVCMOS33;		
NET 485_DI LOC  = R20 | IOSTANDARD=LVCMOS33;		


# Board ID  - inputs
#######################################################
NET P0 LOC  = C4 | IOSTANDARD=LVCMOS33;		
NET P1 LOC  = C5 | IOSTANDARD=LVCMOS33;		
NET P2 LOC  = C6 | IOSTANDARD=LVCMOS33;		
NET P3 LOC  = C7 | IOSTANDARD=LVCMOS33;		
NET P4 LOC  = C8 | IOSTANDARD=LVCMOS33;		
NET P5 LOC  = B8 | IOSTANDARD=LVCMOS33;		
NET P6 LOC  = C9 | IOSTANDARD=LVCMOS33;	
NET P7 LOC  = B9 | IOSTANDARD=LVCMOS33;	


# Board Addresses
#######################################################
NET ADDR0 LOC  = A15 | IOSTANDARD=LVCMOS33;
NET ADDR1 LOC  = B15 | IOSTANDARD=LVCMOS33;
NET ADDR2 LOC  = A16 | IOSTANDARD=LVCMOS33;
NET ADDR3 LOC  = A17 | IOSTANDARD=LVCMOS33;
NET ADDR4 LOC  = A18 | IOSTANDARD=LVCMOS33;
NET ADDR5 LOC  = B18 | IOSTANDARD=LVCMOS33;


# DAC SPI Interface
#######################################################
NET MOSI LOC  = E20 | IOSTANDARD=LVCMOS33;			
NET SCK LOC  = E19 | IOSTANDARD=LVCMOS33;			
NET DAC_CS LOC  = E18 | IOSTANDARD=LVCMOS33;			
NET DAC_CRL LOC  = D20 | IOSTANDARD=LVCMOS33;			


# Testpoints
######################################################
# on Connector J5
NET TP0_0 LOC  = B3 | IOSTANDARD=LVCMOS33;
NET TP1_0 LOC  = A3 | IOSTANDARD=LVCMOS33;
NET TP2_0 LOC  = A4 | IOSTANDARD=LVCMOS33;
NET TP3_0 LOC  = B5 | IOSTANDARD=LVCMOS33;

# on Connector J6
NET TP4_0 LOC  = A5 | IOSTANDARD=LVCMOS33;
NET TP5_0 LOC  = A6 | IOSTANDARD=LVCMOS33;
NET TP6_0 LOC  = B7 | IOSTANDARD=LVCMOS33;
NET TP7_0 LOC  = A7 | IOSTANDARD=LVCMOS33;

# on Connector J7
NET TP8_0 LOC  = B11  | IOSTANDARD=LVCMOS33;
NET TP9_0 LOC  = A12  | IOSTANDARD=LVCMOS33;
NET TP10_0 LOC  = B12 | IOSTANDARD=LVCMOS33;
NET TP11_0 LOC  = A14 | IOSTANDARD=LVCMOS33;


# LVDS Inputs
######################################################
LVDS0_P  LOC  = Y4 | IOSTANDARD=LVCMOS33; # Patch 0
LVDS0_N  LOC  = Y5 | IOSTANDARD=LVCMOS33;

LVDS1_P  LOC  = Y6 | IOSTANDARD=LVCMOS33; # Patch 1
LVDS1_N  LOC  = Y7 | IOSTANDARD=LVCMOS33;

LVDS2_P  LOC  = Y17 | IOSTANDARD=LVCMOS33; # Patch 2
LVDS2_N  LOC  = Y18 | IOSTANDARD=LVCMOS33;

LVDS3_P  LOC  = Y16 | IOSTANDARD=LVCMOS33; # Patch 3
LVDS3_N  LOC  = W16 | IOSTANDARD=LVCMOS33;

TRG_P+   LOC  = Y13 | IOSTANDARD=LVCMOS33; #The Trigger Primitive
TRG_P-   LOC  = W13 | IOSTANDARD=LVCMOS33;





# Enables 
######################################################
# Patch 0
XEN0_0   LOC  = D2 | IOSTANDARD=LVCMOS33;
XEN0_1   LOC  = B1 | IOSTANDARD=LVCMOS33;
XEN0_2   LOC  = C2 | IOSTANDARD=LVCMOS33;
XEN0_3   LOC  = D1 | IOSTANDARD=LVCMOS33;
XEN0_4   LOC  = C1 | IOSTANDARD=LVCMOS33;
XEN0_5   LOC  = D4 | IOSTANDARD=LVCMOS33;
XEN0_6   LOC  = E1 | IOSTANDARD=LVCMOS33;
XEN0_7   LOC  = D3 | IOSTANDARD=LVCMOS33;
XEN0_8   LOC  = E3 | IOSTANDARD=LVCMOS33;

# Patch 1
XEN1_0   LOC  = F2 | IOSTANDARD=LVCMOS33;
XEN1_1   LOC  = F4 | IOSTANDARD=LVCMOS33;
XEN1_2   LOC  = F3 | IOSTANDARD=LVCMOS33;
XEN1_3   LOC  = F1 | IOSTANDARD=LVCMOS33;
XEN1_4   LOC  = G3 | IOSTANDARD=LVCMOS33;
XEN1_5   LOC  = G4 | IOSTANDARD=LVCMOS33;
XEN1_6   LOC  = H2 | IOSTANDARD=LVCMOS33;
XEN1_7   LOC  = H3 | IOSTANDARD=LVCMOS33;
XEN1_8   LOC  = J3 | IOSTANDARD=LVCMOS33;

# Patch 2
XEN2_0   LOC  = N1 | IOSTANDARD=LVCMOS33;
XEN2_1   LOC  = R1 | IOSTANDARD=LVCMOS33;
XEN2_2   LOC  = M3 | IOSTANDARD=LVCMOS33;
XEN2_3   LOC  = N2 | IOSTANDARD=LVCMOS33;
XEN2_4   LOC  = P1 | IOSTANDARD=LVCMOS33;
XEN2_5   LOC  = N3 | IOSTANDARD=LVCMOS33;
XEN2_6   LOC  = R2 | IOSTANDARD=LVCMOS33;
XEN2_7   LOC  = P3 | IOSTANDARD=LVCMOS33;
XEN2_8   LOC  = T2 | IOSTANDARD=LVCMOS33;

# Patch 3
XEN2_0   LOC  = R3 | IOSTANDARD=LVCMOS33;
XEN2_1   LOC  = T4 | IOSTANDARD=LVCMOS33;
XEN2_2   LOC  = T3 | IOSTANDARD=LVCMOS33;
XEN2_3   LOC  = U1 | IOSTANDARD=LVCMOS33;
XEN2_4   LOC  = U3 | IOSTANDARD=LVCMOS33;
XEN2_5   LOC  = V1 | IOSTANDARD=LVCMOS33;
XEN2_6   LOC  = V2 | IOSTANDARD=LVCMOS33;
XEN2_7   LOC  = W1 | IOSTANDARD=LVCMOS33;
XEN2_8   LOC  = W2 | IOSTANDARD=LVCMOS33;