source: FPGA/FTU/ftu_board.ucf @ 219

Last change on this file since 219 was 219, checked in by pavogler, 11 years ago
FTU pin location added
File size: 4.3 KB
Line 
1########################################################
2# FTU Board
3# FACT Trigger Unit
4#
5# Pin location constraints
6#
7# by Patrick Vogler
8########################################################
9
10
11#Clock
12#######################################################
13NET Clk LOC = Y11 | IOSTANDARD=LVCMOS33;               
14
15
16# RS-485 Interface
17#######################################################
18NET 485_RE LOC  = T20 | IOSTANDARD=LVCMOS33;           
19NET 485_DE LOC  = U20 | IOSTANDARD=LVCMOS33;           
20NET 485_DO LOC  = U19 | IOSTANDARD=LVCMOS33;           
21NET 485_DI LOC  = R20 | IOSTANDARD=LVCMOS33;           
22
23
24# Board ID  - inputs
25#######################################################
26NET P0 LOC  = C4 | IOSTANDARD=LVCMOS33;         
27NET P1 LOC  = C5 | IOSTANDARD=LVCMOS33;         
28NET P2 LOC  = C6 | IOSTANDARD=LVCMOS33;         
29NET P3 LOC  = C7 | IOSTANDARD=LVCMOS33;         
30NET P4 LOC  = C8 | IOSTANDARD=LVCMOS33;         
31NET P5 LOC  = B8 | IOSTANDARD=LVCMOS33;         
32NET P6 LOC  = C9 | IOSTANDARD=LVCMOS33;
33NET P7 LOC  = B9 | IOSTANDARD=LVCMOS33;
34
35
36# Board Addresses
37#######################################################
38NET ADDR0 LOC  = A15 | IOSTANDARD=LVCMOS33;
39NET ADDR1 LOC  = B15 | IOSTANDARD=LVCMOS33;
40NET ADDR2 LOC  = A16 | IOSTANDARD=LVCMOS33;
41NET ADDR3 LOC  = A17 | IOSTANDARD=LVCMOS33;
42NET ADDR4 LOC  = A18 | IOSTANDARD=LVCMOS33;
43NET ADDR5 LOC  = B18 | IOSTANDARD=LVCMOS33;
44
45
46# DAC SPI Interface
47#######################################################
48NET MOSI LOC  = E20 | IOSTANDARD=LVCMOS33;                     
49NET SCK LOC  = E19 | IOSTANDARD=LVCMOS33;                       
50NET DAC_CS LOC  = E18 | IOSTANDARD=LVCMOS33;                   
51NET DAC_CRL LOC  = D20 | IOSTANDARD=LVCMOS33;                   
52
53
54# Testpoints
55######################################################
56# on Connector J5
57NET TP0_0 LOC  = B3 | IOSTANDARD=LVCMOS33;
58NET TP1_0 LOC  = A3 | IOSTANDARD=LVCMOS33;
59NET TP2_0 LOC  = A4 | IOSTANDARD=LVCMOS33;
60NET TP3_0 LOC  = B5 | IOSTANDARD=LVCMOS33;
61
62# on Connector J6
63NET TP4_0 LOC  = A5 | IOSTANDARD=LVCMOS33;
64NET TP5_0 LOC  = A6 | IOSTANDARD=LVCMOS33;
65NET TP6_0 LOC  = B7 | IOSTANDARD=LVCMOS33;
66NET TP7_0 LOC  = A7 | IOSTANDARD=LVCMOS33;
67
68# on Connector J7
69NET TP8_0 LOC  = B11  | IOSTANDARD=LVCMOS33;
70NET TP9_0 LOC  = A12  | IOSTANDARD=LVCMOS33;
71NET TP10_0 LOC  = B12 | IOSTANDARD=LVCMOS33;
72NET TP11_0 LOC  = A14 | IOSTANDARD=LVCMOS33;
73
74
75# LVDS Inputs
76######################################################
77LVDS0_P  LOC  = Y4 | IOSTANDARD=LVCMOS33; # Patch 0
78LVDS0_N  LOC  = Y5 | IOSTANDARD=LVCMOS33;
79
80LVDS1_P  LOC  = Y6 | IOSTANDARD=LVCMOS33; # Patch 1
81LVDS1_N  LOC  = Y7 | IOSTANDARD=LVCMOS33;
82
83LVDS2_P  LOC  = Y17 | IOSTANDARD=LVCMOS33; # Patch 2
84LVDS2_N  LOC  = Y18 | IOSTANDARD=LVCMOS33;
85
86LVDS3_P  LOC  = Y16 | IOSTANDARD=LVCMOS33; # Patch 3
87LVDS3_N  LOC  = W16 | IOSTANDARD=LVCMOS33;
88
89TRG_P+   LOC  = Y13 | IOSTANDARD=LVCMOS33; #The Trigger Primitive
90TRG_P-   LOC  = W13 | IOSTANDARD=LVCMOS33;
91
92
93
94
95
96# Enables
97######################################################
98# Patch 0
99XEN0_0   LOC  = D2 | IOSTANDARD=LVCMOS33;
100XEN0_1   LOC  = B1 | IOSTANDARD=LVCMOS33;
101XEN0_2   LOC  = C2 | IOSTANDARD=LVCMOS33;
102XEN0_3   LOC  = D1 | IOSTANDARD=LVCMOS33;
103XEN0_4   LOC  = C1 | IOSTANDARD=LVCMOS33;
104XEN0_5   LOC  = D4 | IOSTANDARD=LVCMOS33;
105XEN0_6   LOC  = E1 | IOSTANDARD=LVCMOS33;
106XEN0_7   LOC  = D3 | IOSTANDARD=LVCMOS33;
107XEN0_8   LOC  = E3 | IOSTANDARD=LVCMOS33;
108
109# Patch 1
110XEN1_0   LOC  = F2 | IOSTANDARD=LVCMOS33;
111XEN1_1   LOC  = F4 | IOSTANDARD=LVCMOS33;
112XEN1_2   LOC  = F3 | IOSTANDARD=LVCMOS33;
113XEN1_3   LOC  = F1 | IOSTANDARD=LVCMOS33;
114XEN1_4   LOC  = G3 | IOSTANDARD=LVCMOS33;
115XEN1_5   LOC  = G4 | IOSTANDARD=LVCMOS33;
116XEN1_6   LOC  = H2 | IOSTANDARD=LVCMOS33;
117XEN1_7   LOC  = H3 | IOSTANDARD=LVCMOS33;
118XEN1_8   LOC  = J3 | IOSTANDARD=LVCMOS33;
119
120# Patch 2
121XEN2_0   LOC  = N1 | IOSTANDARD=LVCMOS33;
122XEN2_1   LOC  = R1 | IOSTANDARD=LVCMOS33;
123XEN2_2   LOC  = M3 | IOSTANDARD=LVCMOS33;
124XEN2_3   LOC  = N2 | IOSTANDARD=LVCMOS33;
125XEN2_4   LOC  = P1 | IOSTANDARD=LVCMOS33;
126XEN2_5   LOC  = N3 | IOSTANDARD=LVCMOS33;
127XEN2_6   LOC  = R2 | IOSTANDARD=LVCMOS33;
128XEN2_7   LOC  = P3 | IOSTANDARD=LVCMOS33;
129XEN2_8   LOC  = T2 | IOSTANDARD=LVCMOS33;
130
131# Patch 3
132XEN2_0   LOC  = R3 | IOSTANDARD=LVCMOS33;
133XEN2_1   LOC  = T4 | IOSTANDARD=LVCMOS33;
134XEN2_2   LOC  = T3 | IOSTANDARD=LVCMOS33;
135XEN2_3   LOC  = U1 | IOSTANDARD=LVCMOS33;
136XEN2_4   LOC  = U3 | IOSTANDARD=LVCMOS33;
137XEN2_5   LOC  = V1 | IOSTANDARD=LVCMOS33;
138XEN2_6   LOC  = V2 | IOSTANDARD=LVCMOS33;
139XEN2_7   LOC  = W1 | IOSTANDARD=LVCMOS33;
140XEN2_8   LOC  = W2 | IOSTANDARD=LVCMOS33;
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