source: FPGA/FTU/ip_cores/FTU_dac_dcm.vhd @ 156

Last change on this file since 156 was 156, checked in by qweitzel, 11 years ago
First check-in of VHDL code for FTU: counters, dcm, spi
File size: 2.8 KB
Line 
1--------------------------------------------------------------------------------
2-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3--------------------------------------------------------------------------------
4--   ____  ____
5--  /   /\/   /
6-- /___/  \  /    Vendor: Xilinx
7-- \   \   \/     Version : 11.1
8--  \   \         Application : xaw2vhdl
9--  /   /         Filename : FTU_dac_dcm.vhd
10-- /___/   /\     Timestamp : 01/20/2010 16:36:17
11-- \   \  /  \
12--  \___\/\___\
13--
14--Command: xaw2vhdl-st /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm.xaw /home/qweitzel/FPGA/FACT/FTU/source/ip_cores/FTU_dac_dcm
15--Design Name: FTU_dac_dcm
16--Device: xc3s400an-4fgg400
17--
18-- Module FTU_dac_dcm
19-- Generated by Xilinx Architecture Wizard
20-- Written for synthesis tool: XST
21-- Period Jitter (unit interval) for block DCM_SP_INST = 0.03 UI
22-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 6.54 ns
23
24library ieee;
25use ieee.std_logic_1164.ALL;
26use ieee.numeric_std.ALL;
27library UNISIM;
28use UNISIM.Vcomponents.ALL;
29
30entity FTU_dac_dcm is
31   port ( CLKIN_IN        : in    std_logic; 
32          RST_IN          : in    std_logic; 
33          CLKFX_OUT       : out   std_logic; 
34          CLKIN_IBUFG_OUT : out   std_logic; 
35          LOCKED_OUT      : out   std_logic);
36end FTU_dac_dcm;
37
38architecture BEHAVIORAL of FTU_dac_dcm is
39   signal CLKFX_BUF       : std_logic;
40   signal CLKIN_IBUFG     : std_logic;
41   signal GND_BIT         : std_logic;
42begin
43   GND_BIT <= '0';
44   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
45   CLKFX_BUFG_INST : BUFG
46      port map (I=>CLKFX_BUF,
47                O=>CLKFX_OUT);
48   
49   CLKIN_IBUFG_INST : IBUFG
50      port map (I=>CLKIN_IN,
51                O=>CLKIN_IBUFG);
52   
53   DCM_SP_INST : DCM_SP
54   generic map( CLK_FEEDBACK => "NONE",
55            CLKDV_DIVIDE => 2.0,
56            CLKFX_DIVIDE => 20,
57            CLKFX_MULTIPLY => 2,
58            CLKIN_DIVIDE_BY_2 => FALSE,
59            CLKIN_PERIOD => 20.000,
60            CLKOUT_PHASE_SHIFT => "NONE",
61            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
62            DFS_FREQUENCY_MODE => "LOW",
63            DLL_FREQUENCY_MODE => "LOW",
64            DUTY_CYCLE_CORRECTION => TRUE,
65            FACTORY_JF => x"C080",
66            PHASE_SHIFT => 0,
67            STARTUP_WAIT => FALSE)
68      port map (CLKFB=>GND_BIT,
69                CLKIN=>CLKIN_IBUFG,
70                DSSEN=>GND_BIT,
71                PSCLK=>GND_BIT,
72                PSEN=>GND_BIT,
73                PSINCDEC=>GND_BIT,
74                RST=>RST_IN,
75                CLKDV=>open,
76                CLKFX=>CLKFX_BUF,
77                CLKFX180=>open,
78                CLK0=>open,
79                CLK2X=>open,
80                CLK2X180=>open,
81                CLK90=>open,
82                CLK180=>open,
83                CLK270=>open,
84                LOCKED=>LOCKED_OUT,
85                PSDONE=>open,
86                STATUS=>open);
87   
88end BEHAVIORAL;
89
90
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