Last change
on this file since 9223 was 156, checked in by qweitzel, 15 years ago |
First check-in of VHDL code for FTU: counters, dcm, spi
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File size:
952 bytes
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1 | -- File: upcnt16.vhd
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2 | --
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3 | -- Purpose: Up 16-bit counter
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4 | --
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5 | -- Created: 7-25-00 ALS
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6 | --
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7 |
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8 | library IEEE;
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9 | use IEEE.std_logic_1164.all;
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10 | use IEEE.std_logic_arith.all;
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11 |
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12 | entity upcnt16 is
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13 | port(
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14 | full : out STD_LOGIC;
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15 | clr : in STD_LOGIC;
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16 | reset : in STD_Logic;
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17 | clk : in STD_LOGIC
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18 | );
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19 |
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20 | end upcnt16;
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21 |
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22 | architecture DEFINITION of upcnt16 is
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23 |
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24 | constant RESET_ACTIVE : std_logic := '0';
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25 | constant Cnt_full : Unsigned (15 DOWNTO 0) :="1111111111111111";
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26 |
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27 | signal q : Unsigned (15 DOWNTO 0);
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28 |
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29 | begin
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30 |
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31 | process(clk, reset, clr)
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32 | begin
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33 |
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34 | if ((reset OR clr)='1') then
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35 | q <= (others => '0');-- Clear output register
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36 | elsif (clk'event) and clk = '1' and (not(q = Cnt_full)) then-- On rising edge of clock count
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37 | q <= q + 1;
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38 | end if;
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39 |
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40 | end process;
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41 |
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42 | process(q)
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43 | begin
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44 |
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45 | if (q = Cnt_full) then
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46 | full <= '1';
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47 | else
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48 | full <= '0';
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49 | end if;
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50 |
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51 | end process;
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52 |
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53 | end DEFINITION;
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