source: FPGA/FTU/old_design/counter/upcnt5.vhd@ 9223

Last change on this file since 9223 was 156, checked in by qweitzel, 15 years ago
First check-in of VHDL code for FTU: counters, dcm, spi
File size: 1.7 KB
Line 
1-- File: upcnt5.vhd
2--
3-- Author: Jennifer Jenkins
4-- Purpose: Up 5-bit counter
5--
6-- Created: 5-3-99 JLJ
7-- Revised: 6-15-99 ALS
8
9---------------------------------------------------------------------------------------------
10---------------------------------------------------------------------------------------------
11-- Modified by Patrick Vogler
12-- 18th November 2009
13--
14-- Counter width extended from 4 to 5 bit in order to extend the SPI interface from
15-- 8 to 16 bit word size
16--
17-- Modifications are marked by: *Mod: <modification>
18--
19-- Cleaned up by Quirin Weitzel
20-- 21th January 2010
21---------------------------------------------------------------------------------------------
22---------------------------------------------------------------------------------------------
23library IEEE;
24use IEEE.std_logic_1164.all;
25use IEEE.std_logic_arith.all;
26
27entity upcnt5 is --*Mod: 4 to 5 bit
28 port(
29 cnt_en : in STD_LOGIC; -- Count enable -- Load line enable
30 clr : in STD_LOGIC; -- Active low clear
31 clk : in STD_LOGIC; -- Clock
32 qout : inout STD_LOGIC_VECTOR (4 downto 0) --*Mod: 4 to 5 bit
33 );
34end upcnt5;
35
36architecture DEFINITION of upcnt5 is
37
38constant RESET_ACTIVE : std_logic := '0';
39
40signal q_int : UNSIGNED (4 downto 0); --*Mod: 4 to 5 bit
41
42begin
43
44 process(clk, clr)
45 begin
46 -- Clear output register
47 if (clr = RESET_ACTIVE) then
48 q_int <= (others => '0');
49 -- On falling edge of clock count
50 elsif (clk'event) and clk = '1' then
51 if cnt_en = '1' then
52 q_int <= q_int + 1;
53 end if;
54 end if;
55 end process;
56
57 qout <= STD_LOGIC_VECTOR(q_int);
58
59end DEFINITION;
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