source: FPGA/FTU/ram/FTU_dual_port_ram.asy@ 408

Last change on this file since 408 was 273, checked in by qweitzel, 14 years ago
new structure for FTU firmware, not yet finished
File size: 1.1 KB
Line 
1Version 4
2SymbolType BLOCK
3TEXT 32 32 LEFT 4 FTU_dual_port_ram
4RECTANGLE Normal 32 32 544 672
5LINE Wide 0 80 32 80
6PIN 0 80 LEFT 36
7PINATTR PinName addra[4:0]
8PINATTR Polarity IN
9LINE Wide 0 112 32 112
10PIN 0 112 LEFT 36
11PINATTR PinName dina[7:0]
12PINATTR Polarity IN
13LINE Normal 0 144 32 144
14PIN 0 144 LEFT 36
15PINATTR PinName ena
16PINATTR Polarity IN
17LINE Wide 0 208 32 208
18PIN 0 208 LEFT 36
19PINATTR PinName wea[0:0]
20PINATTR Polarity IN
21LINE Normal 0 272 32 272
22PIN 0 272 LEFT 36
23PINATTR PinName clka
24PINATTR Polarity IN
25LINE Wide 0 432 32 432
26PIN 0 432 LEFT 36
27PINATTR PinName addrb[3:0]
28PINATTR Polarity IN
29LINE Wide 0 464 32 464
30PIN 0 464 LEFT 36
31PINATTR PinName dinb[15:0]
32PINATTR Polarity IN
33LINE Normal 0 496 32 496
34PIN 0 496 LEFT 36
35PINATTR PinName enb
36PINATTR Polarity IN
37LINE Wide 0 560 32 560
38PIN 0 560 LEFT 36
39PINATTR PinName web[0:0]
40PINATTR Polarity IN
41LINE Normal 0 624 32 624
42PIN 0 624 LEFT 36
43PINATTR PinName clkb
44PINATTR Polarity IN
45LINE Wide 576 80 544 80
46PIN 576 80 RIGHT 36
47PINATTR PinName douta[7:0]
48PINATTR Polarity OUT
49LINE Wide 576 368 544 368
50PIN 576 368 RIGHT 36
51PINATTR PinName doutb[15:0]
52PINATTR Polarity OUT
53
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