source: FPGA/FTU/ram/FTU_dual_port_ram.gise@ 408

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  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FTU_dual_port_ram.xise"/>

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    <file xil_pn:fileType="FILE_VHO" xil_pn:name="FTU_dual_port_ram.vho" xil_pn:origination="imported"/>
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