source: FPGA/FTU/ram/FTU_dual_port_ram.gise@ 9488

Last change on this file since 9488 was 273, checked in by qweitzel, 14 years ago
new structure for FTU firmware, not yet finished
File size: 1.5 KB
Line 
1<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
4 <!-- -->
5
6 <!-- For tool use only. Do not edit. -->
7
8 <!-- -->
9
10 <!-- ProjectNavigator created generated project file. -->
11
12 <!-- For use in tracking generated file and other information -->
13
14 <!-- allowing preservation of process status. -->
15
16 <!-- -->
17
18 <!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
19
20 <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
21
22 <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FTU_dual_port_ram.xise"/>
23
24 <files xmlns="http://www.xilinx.com/XMLSchema">
25 <file xil_pn:fileType="FILE_ASY" xil_pn:name="FTU_dual_port_ram.asy" xil_pn:origination="imported"/>
26 <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="FTU_dual_port_ram.sym" xil_pn:origination="imported"/>
27 <file xil_pn:fileType="FILE_VEO" xil_pn:name="FTU_dual_port_ram.veo" xil_pn:origination="imported"/>
28 <file xil_pn:fileType="FILE_VHO" xil_pn:name="FTU_dual_port_ram.vho" xil_pn:origination="imported"/>
29 </files>
30
31 <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
32
33</generated_project>
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