source: FPGA/FTU/ram/FTU_dual_port_ram.v@ 827

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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file FTU_dual_port_ram.v when simulating
// the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module FTU_dual_port_ram(
        clka,
        ena,
        wea,
        addra,
        dina,
        douta,
        clkb,
        enb,
        web,
        addrb,
        dinb,
        doutb);


input clka;
input ena;
input [0 : 0] wea;
input [4 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [3 : 0] addrb;
input [15 : 0] dinb;
output [15 : 0] doutb;

// synthesis translate_off

      BLK_MEM_GEN_V3_3 #(
                .C_ADDRA_WIDTH(5),
                .C_ADDRB_WIDTH(4),
                .C_ALGORITHM(2),
                .C_BYTE_SIZE(9),
                .C_COMMON_CLK(0),
                .C_DEFAULT_DATA("0"),
                .C_DISABLE_WARN_BHV_COLL(0),
                .C_DISABLE_WARN_BHV_RANGE(0),
                .C_FAMILY("spartan3"),
                .C_HAS_ENA(1),
                .C_HAS_ENB(1),
                .C_HAS_INJECTERR(0),
                .C_HAS_MEM_OUTPUT_REGS_A(0),
                .C_HAS_MEM_OUTPUT_REGS_B(0),
                .C_HAS_MUX_OUTPUT_REGS_A(0),
                .C_HAS_MUX_OUTPUT_REGS_B(0),
                .C_HAS_REGCEA(0),
                .C_HAS_REGCEB(0),
                .C_HAS_RSTA(0),
                .C_HAS_RSTB(0),
                .C_INITA_VAL("0"),
                .C_INITB_VAL("0"),
                .C_INIT_FILE_NAME("no_coe_file_loaded"),
                .C_LOAD_INIT_FILE(0),
                .C_MEM_TYPE(2),
                .C_MUX_PIPELINE_STAGES(0),
                .C_PRIM_TYPE(1),
                .C_READ_DEPTH_A(32),
                .C_READ_DEPTH_B(16),
                .C_READ_WIDTH_A(8),
                .C_READ_WIDTH_B(16),
                .C_RSTRAM_A(0),
                .C_RSTRAM_B(0),
                .C_RST_PRIORITY_A("CE"),
                .C_RST_PRIORITY_B("CE"),
                .C_RST_TYPE("SYNC"),
                .C_SIM_COLLISION_CHECK("ALL"),
                .C_USE_BYTE_WEA(0),
                .C_USE_BYTE_WEB(0),
                .C_USE_DEFAULT_DATA(0),
                .C_USE_ECC(0),
                .C_WEA_WIDTH(1),
                .C_WEB_WIDTH(1),
                .C_WRITE_DEPTH_A(32),
                .C_WRITE_DEPTH_B(16),
                .C_WRITE_MODE_A("NO_CHANGE"),
                .C_WRITE_MODE_B("NO_CHANGE"),
                .C_WRITE_WIDTH_A(8),
                .C_WRITE_WIDTH_B(16),
                .C_XDEVICEFAMILY("spartan3a"))
        inst (
                .CLKA(clka),
                .ENA(ena),
                .WEA(wea),
                .ADDRA(addra),
                .DINA(dina),
                .DOUTA(douta),
                .CLKB(clkb),
                .ENB(enb),
                .WEB(web),
                .ADDRB(addrb),
                .DINB(dinb),
                .DOUTB(doutb),
                .RSTA(),
                .REGCEA(),
                .RSTB(),
                .REGCEB(),
                .INJECTSBITERR(),
                .INJECTDBITERR(),
                .SBITERR(),
                .DBITERR(),
                .RDADDRECC());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of FTU_dual_port_ram is "black_box"

endmodule