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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
FTU_dual_port_ram YourInstanceName (
	.clka(clka),
	.ena(ena),
	.wea(wea), // Bus [0 : 0] 
	.addra(addra), // Bus [4 : 0] 
	.dina(dina), // Bus [7 : 0] 
	.douta(douta), // Bus [7 : 0] 
	.clkb(clkb),
	.enb(enb),
	.web(web), // Bus [0 : 0] 
	.addrb(addrb), // Bus [3 : 0] 
	.dinb(dinb), // Bus [15 : 0] 
	.doutb(doutb)); // Bus [15 : 0] 

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file FTU_dual_port_ram.v when simulating
// the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".