| 1 | /*******************************************************************************
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| 2 | * This file is owned and controlled by Xilinx and must be used *
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| 3 | * solely for design, simulation, implementation and creation of *
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| 4 | * design files limited to Xilinx devices or technologies. Use *
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| 5 | * with non-Xilinx devices or technologies is expressly prohibited *
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| 6 | * and immediately terminates your license. *
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| 7 | * *
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| 8 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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| 9 | * SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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| 10 | * XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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| 11 | * AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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| 12 | * OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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| 13 | * IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
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| 14 | * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
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| 15 | * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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| 16 | * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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| 17 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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| 18 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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| 19 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
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| 20 | * FOR A PARTICULAR PURPOSE. *
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| 21 | * *
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| 22 | * Xilinx products are not intended for use in life support *
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| 23 | * appliances, devices, or systems. Use in such applications are *
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| 24 | * expressly prohibited. *
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| 25 | * *
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| 26 | * (c) Copyright 1995-2009 Xilinx, Inc. *
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| 27 | * All rights reserved. *
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| 28 | *******************************************************************************/
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| 29 | // The following must be inserted into your Verilog file for this
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| 30 | // core to be instantiated. Change the instance name and port connections
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| 31 | // (in parentheses) to your own signal names.
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| 32 |
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| 33 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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| 34 | FTU_dual_port_ram YourInstanceName (
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| 35 | .clka(clka),
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| 36 | .ena(ena),
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| 37 | .wea(wea), // Bus [0 : 0]
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| 38 | .addra(addra), // Bus [4 : 0]
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| 39 | .dina(dina), // Bus [7 : 0]
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| 40 | .douta(douta), // Bus [7 : 0]
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| 41 | .clkb(clkb),
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| 42 | .enb(enb),
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| 43 | .web(web), // Bus [0 : 0]
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| 44 | .addrb(addrb), // Bus [3 : 0]
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| 45 | .dinb(dinb), // Bus [15 : 0]
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| 46 | .doutb(doutb)); // Bus [15 : 0]
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| 47 |
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| 48 | // INST_TAG_END ------ End INSTANTIATION Template ---------
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| 49 |
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| 50 | // You must compile the wrapper file FTU_dual_port_ram.v when simulating
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| 51 | // the core, FTU_dual_port_ram. When compiling the wrapper file, be sure to
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| 52 | // reference the XilinxCoreLib Verilog simulation library. For detailed
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| 53 | // instructions, please refer to the "CORE Generator Help".
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| 54 |
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