| 1 | ##############################################################
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| 2 | #
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| 3 | # Xilinx Core Generator version 11.5
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| 4 | # Date: Tue Jul 13 08:58:12 2010
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| 5 | #
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| 6 | ##############################################################
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| 7 | #
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| 8 | # This file contains the customisation parameters for a
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| 9 | # Xilinx CORE Generator IP GUI. It is strongly recommended
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| 10 | # that you do not manually alter this file as it may cause
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| 11 | # unexpected and unsupported behavior.
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| 12 | #
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| 13 | ##############################################################
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| 14 | #
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| 15 | # BEGIN Project Options
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| 16 | SET addpads = False
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| 17 | SET asysymbol = True
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| 18 | SET busformat = BusFormatAngleBracketNotRipped
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| 19 | SET createndf = False
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| 20 | SET designentry = VHDL
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| 21 | SET device = xc3s400an
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| 22 | SET devicefamily = spartan3a
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| 23 | SET flowvendor = Foundation_ISE
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| 24 | SET formalverification = False
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| 25 | SET foundationsym = False
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| 26 | SET implementationfiletype = Ngc
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| 27 | SET package = fgg400
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| 28 | SET removerpms = False
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| 29 | SET simulationfiles = Behavioral
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| 30 | SET speedgrade = -4
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| 31 | SET verilogsim = True
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| 32 | SET vhdlsim = True
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| 33 | # END Project Options
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| 34 | # BEGIN Select
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| 35 | SELECT Block_Memory_Generator family Xilinx,_Inc. 3.3
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| 36 | # END Select
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| 37 | # BEGIN Parameters
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| 38 | CSET additional_inputs_for_power_estimation=false
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| 39 | CSET algorithm=Low_Power
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| 40 | CSET assume_synchronous_clk=false
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| 41 | CSET byte_size=9
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| 42 | CSET coe_file=no_coe_file_loaded
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| 43 | CSET collision_warnings=ALL
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| 44 | CSET component_name=FTU_dual_port_ram
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| 45 | CSET disable_collision_warnings=false
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| 46 | CSET disable_out_of_range_warnings=false
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| 47 | CSET ecc=false
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| 48 | CSET enable_a=Use_ENA_Pin
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| 49 | CSET enable_b=Use_ENB_Pin
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| 50 | CSET error_injection_type=Single_Bit_Error_Injection
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| 51 | CSET fill_remaining_memory_locations=false
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| 52 | CSET load_init_file=false
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| 53 | CSET memory_type=True_Dual_Port_RAM
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| 54 | CSET operating_mode_a=NO_CHANGE
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| 55 | CSET operating_mode_b=NO_CHANGE
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| 56 | CSET output_reset_value_a=0
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| 57 | CSET output_reset_value_b=0
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| 58 | CSET pipeline_stages=0
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| 59 | CSET port_a_clock=100
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| 60 | CSET port_a_enable_rate=100
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| 61 | CSET port_a_write_rate=50
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| 62 | CSET port_b_clock=100
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| 63 | CSET port_b_enable_rate=100
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| 64 | CSET port_b_write_rate=50
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| 65 | CSET primitive=8kx2
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| 66 | CSET read_width_a=8
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| 67 | CSET read_width_b=16
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| 68 | CSET register_porta_output_of_memory_core=false
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| 69 | CSET register_porta_output_of_memory_primitives=false
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| 70 | CSET register_portb_output_of_memory_core=false
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| 71 | CSET register_portb_output_of_memory_primitives=false
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| 72 | CSET remaining_memory_locations=0
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| 73 | CSET reset_memory_latch_a=false
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| 74 | CSET reset_memory_latch_b=false
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| 75 | CSET reset_priority_a=CE
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| 76 | CSET reset_priority_b=CE
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| 77 | CSET reset_type=SYNC
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| 78 | CSET use_byte_write_enable=false
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| 79 | CSET use_error_injection_pins=false
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| 80 | CSET use_regcea_pin=false
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| 81 | CSET use_regceb_pin=false
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| 82 | CSET use_rsta_pin=false
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| 83 | CSET use_rstb_pin=false
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| 84 | CSET write_depth_a=32
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| 85 | CSET write_width_a=8
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| 86 | CSET write_width_b=16
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| 87 | # END Parameters
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| 88 | GENERATE
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| 89 | # CRC: 54a45d78
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