source: FPGA/FTU/spi_interface/spi_xmit_shift_reg_16.vhd @ 156

Last change on this file since 156 was 156, checked in by qweitzel, 11 years ago
First check-in of VHDL code for FTU: counters, dcm, spi
File size: 3.8 KB
Line 
1---------------------------------------------------------------------------------------------
2---------------------------------------------------------------------------------------------
3--  File:          spi_xmit_shift_reg_16.vhd
4--
5--
6--  Original file: spi_xmit_shift_reg.vhd
7--
8--  Created:  9-6-00 ALS
9--  SPI shift register that shifts data out on MOSI. No data is shifted in.
10--  This is an 8-bit, loadable register. The data output from the shift register is
11--  clocked one additional system clock to align the data with the outgoing clock on
12--  SCK.
13--
14--  Revised: 9-11-00 ALS
15--  Revised: 9-20-00 ALS
16
17---------------------------------------------------------------------------------------------
18---------------------------------------------------------------------------------------------
19--  Modified from 8 to 16 bit word size by Patrick Vogler
20--  18th November 2009
21--
22--       Modifications are marked by: *Mod: <modification>
23--
24--  Cleaned up by Quirin Weitzel
25--  21th January 2010
26---------------------------------------------------------------------------------------------
27---------------------------------------------------------------------------------------------
28library IEEE;
29use IEEE.std_logic_1164.all;
30use IEEE.std_logic_arith.all;
31
32entity spi_xmit_shift_reg is
33  port(
34    data_ld      : in STD_LOGIC;                      -- Data load enable
35    data_in      : in STD_LOGIC_VECTOR (15 downto 0); -- Data to load in, *Mod: 15 instead of 7, parallel input extended from 8 to 16 bit
36    shift_in     : in STD_LOGIC;                      -- Serial data in
37    shift_en     : in STD_LOGIC;                      -- Shift enable         
38    mosi         : out STD_LOGIC;                     -- Shift serial data out
39    ss_in_int    : in STD_LOGIC;                      -- another master is on bus
40    reset        : in STD_LOGIC;                      -- reset
41    sclk         : in STD_LOGIC;                      -- clock
42    sys_clk      : in STD_LOGIC                       -- system clock
43  );
44       
45end spi_xmit_shift_reg;
46
47architecture DEFINITION of spi_xmit_shift_reg is
48
49--******************************** Constants ***********************
50constant RESET_ACTIVE : std_logic := '0';
51
52--******************************** Signals *************************
53signal data_int     : STD_LOGIC_VECTOR (15 downto 0);-- *Mod: 15 instead of 7, parallel output extended from 8 to 16 bit
54signal mosi_int     : STD_LOGIC;
55
56begin
57
58  --******************************** SPI Xmit Shift Register ***********************
59  -- This shift register is clocked on SCK_1
60  xmit_shift_reg:  process(sclk, reset, ss_in_int)
61  begin   
62    -- Clear output register
63    if (reset = RESET_ACTIVE or ss_in_int = '0') then
64      data_int <= (others => '0');
65           
66      -- On rising edge of spi clock, shift data
67    elsif sclk'event and sclk = '1' then
68
69      -- Load data
70      if (data_ld = '1') then
71        data_int <= data_in;
72
73        -- If shift enable is high
74      elsif shift_en = '1' then
75
76        -- Shift the data
77        data_int <= data_int(14 downto 0) & shift_in; --*Mod: 14 instead of 6, shift register extended from 8 to 16 bit
78      end if;
79     
80    end if;
81
82  end process;
83
84  --******************************** MOSI Output Register ***********************
85  -- This output register is clocked on the system clock and aligns the data from the
86  -- shift register with the outgoing SCK
87  outreg: process (sys_clk, reset)
88  begin
89    if reset = RESET_ACTIVE then
90      mosi_int <= '0';
91    elsif sys_clk'event and sys_clk = '1' then
92     
93      mosi_int <= data_int(15); -- *Mod: 15 instead of 7, shift register extended form 8 to 16 bit
94    end if;
95  end process;
96
97  -- The MOSI output is 3-stated if the SS_IN_INT signal is asserted indicating that another
98  -- master is on the bus
99  mosi <= mosi_int when ss_in_int = '1' 
100          else    'Z';
101
102end DEFINITION;
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