source: FPGA/FTU/test_firmware/FTU_test1/FTU_test1.vhd@ 1565

Last change on this file since 1565 was 234, checked in by qweitzel, 15 years ago
ucf file for FTU updated
File size: 6.0 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 04/05/2010
6-- Design Name:
7-- Module Name: FTU_test1 - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Test firmware for FTU board, switch on/off enable signals
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26---- Uncomment the following library declaration if instantiating
27---- any Xilinx primitives in this code.
28--library UNISIM;
29--use UNISIM.VComponents.all;
30
31entity FTU_test1 is
32 port(
33 -- global control
34 ext_clk : IN STD_LOGIC; -- external clock from FTU board
35 --reset : in STD_LOGIC; -- reset
36 brd_add : IN STD_LOGIC_VECTOR(5 downto 0); -- geographic board/slot address
37 brd_id : IN STD_LOGIC_VECTOR(7 downto 0); -- local solder-programmable board ID
38
39 -- rate counters LVDS inputs
40 -- use IBUFDS differential input buffer
41 patch_A_p : IN STD_LOGIC; -- logic signal from first trigger patch
42 patch_A_n : IN STD_LOGIC;
43 patch_B_p : IN STD_LOGIC; -- logic signal from second trigger patch
44 patch_B_n : IN STD_LOGIC;
45 patch_C_p : IN STD_LOGIC; -- logic signal from third trigger patch
46 patch_C_n : IN STD_LOGIC;
47 patch_D_p : IN STD_LOGIC; -- logic signal from fourth trigger patch
48 patch_D_n : IN STD_LOGIC;
49 trig_prim_p : IN STD_LOGIC; -- logic signal from n-out-of-4 circuit
50 trig_prim_n : IN STD_LOGIC;
51
52 -- DAC interface
53 -- miso : IN STD_LOGIC; -- master-in-slave-out
54 sck : OUT STD_LOGIC; -- serial clock to DAC
55 mosi : OUT STD_LOGIC; -- serial data to DAC, master-out-slave-in
56 clr : OUT STD_LOGIC; -- clear signal to DAC
57 cs_ld : OUT STD_LOGIC; -- chip select or load to DAC
58
59 -- RS-485 interface to FTM
60 rx : IN STD_LOGIC; -- serial data from FTM
61 tx : OUT STD_LOGIC; -- serial data to FTM
62 rx_en : OUT STD_LOGIC; -- enable RS-485 receiver
63 tx_en : OUT STD_LOGIC; -- enable RS-485 transmitter
64
65 -- analog buffer enable
66 enables_A : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
67 enables_B : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
68 enables_C : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
69 enables_D : OUT STD_LOGIC_VECTOR(8 downto 0); -- individual enables for analog inputs
70
71 -- testpoints
72 TP_A : out STD_LOGIC_VECTOR(11 downto 0) -- testpoints
73 );
74end FTU_test1;
75
76architecture Behavioral of FTU_test1 is
77
78 component FTU_test1_dcm
79 port(
80 CLKIN_IN : IN STD_LOGIC;
81 CLKFX_OUT : OUT STD_LOGIC;
82 CLKIN_IBUFG_OUT : OUT STD_LOGIC
83 );
84 end component;
85
86 component Clock_Divider
87 port(
88 clock : IN STD_LOGIC;
89 enable_out : OUT STD_LOGIC
90 );
91 end component;
92
93 signal clk_5M_sig : STD_LOGIC;
94 signal enable_sig : STD_LOGIC;
95
96begin
97
98 Inst_FTU_test1_dcm : FTU_test1_dcm
99 port map(
100 CLKIN_IN => ext_clk,
101 CLKFX_OUT => clk_5M_sig,
102 CLKIN_IBUFG_OUT => open
103 );
104
105 Inst_Clock_Divider : Clock_Divider
106 port map (
107 clock => clk_5M_sig,
108 enable_out => enable_sig
109 );
110
111 enables_A(0) <= enable_sig;
112 enables_A(1) <= enable_sig;
113 enables_A(2) <= enable_sig;
114 enables_A(3) <= enable_sig;
115 enables_A(4) <= enable_sig;
116 enables_A(5) <= enable_sig;
117 enables_A(6) <= enable_sig;
118 enables_A(7) <= enable_sig;
119 enables_A(8) <= enable_sig;
120
121 enables_B(0) <= enable_sig;
122 enables_B(1) <= enable_sig;
123 enables_B(2) <= enable_sig;
124 enables_B(3) <= enable_sig;
125 enables_B(4) <= enable_sig;
126 enables_B(5) <= enable_sig;
127 enables_B(6) <= enable_sig;
128 enables_B(7) <= enable_sig;
129 enables_B(8) <= enable_sig;
130
131 enables_C(0) <= enable_sig;
132 enables_C(1) <= enable_sig;
133 enables_C(2) <= enable_sig;
134 enables_C(3) <= enable_sig;
135 enables_C(4) <= enable_sig;
136 enables_C(5) <= enable_sig;
137 enables_C(6) <= enable_sig;
138 enables_C(7) <= enable_sig;
139 enables_C(8) <= enable_sig;
140
141 enables_D(0) <= enable_sig;
142 enables_D(1) <= enable_sig;
143 enables_D(2) <= enable_sig;
144 enables_D(3) <= enable_sig;
145 enables_D(4) <= enable_sig;
146 enables_D(5) <= enable_sig;
147 enables_D(6) <= enable_sig;
148 enables_D(7) <= enable_sig;
149 enables_D(8) <= enable_sig;
150
151end Behavioral;
152
153
154library IEEE;
155use IEEE.STD_LOGIC_1164.ALL;
156use IEEE.STD_LOGIC_ARITH.ALL;
157use IEEE.STD_LOGIC_UNSIGNED.ALL;
158
159entity Clock_Divider is
160 port(
161 clock : in std_logic;
162 enable_out: out std_logic
163 );
164end entity Clock_Divider;
165
166architecture RTL of Clock_Divider is
167
168 --constant max_count : integer := 5000000/1000000; -- for simulation
169 constant max_count : integer := 5000000/1; -- for implementation
170 constant final_count : integer := 10;
171
172begin
173
174 process(clock)
175 variable count : integer range 0 to max_count;
176 variable count2 : integer range 0 to final_count;
177 begin
178 if rising_edge(clock) then
179 --enable_out <= '0';
180 if count2 = final_count then
181 enable_out <= '0';
182 else
183 if count < max_count/2 then
184 enable_out <= '0';
185 count := count + 1;
186 elsif count < max_count then
187 enable_out <= '1';
188 count := count + 1;
189 else
190 count := 0;
191 enable_out <= '0';
192 count2 := count2 + 1;
193 end if;
194 end if;
195 end if;
196 end process;
197
198end architecture RTL;
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