| 1 | ########################################################
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| 2 | # FTU Board
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| 3 | # FACT Trigger Unit
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| 4 | #
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| 5 | # Pin location constraints
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| 6 | #
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| 7 | # by Patrick Vogler, Quirin Weitzel
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| 8 | # 01 July 2010
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| 9 | ########################################################
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| 10 |
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| 11 |
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| 12 | #Clock
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| 13 | #######################################################
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| 14 | NET ext_clk LOC = Y11 | IOSTANDARD=LVCMOS33; # Clk
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| 15 |
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| 16 |
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| 17 | # RS-485 Interface
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| 18 | #######################################################
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| 19 | #NET rx_en LOC = T20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_RE: enable RS-485 receiver
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| 20 | #NET tx_en LOC = U20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DE: enable RS-485 transmitter
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| 21 | #NET tx LOC = U19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # 485_DO: serial data to FTM
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| 22 | #NET rx LOC = R20 | IOSTANDARD=LVCMOS33; # 485_DI: serial data from FTM
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| 23 |
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| 24 |
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| 25 | # Board ID - inputs
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| 26 | # local board-ID "solder programmable"
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| 27 | #######################################################
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| 28 | #NET brd_id<0> LOC = C4 | IOSTANDARD=LVCMOS33; # P0
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| 29 | #NET brd_id<1> LOC = C5 | IOSTANDARD=LVCMOS33; # P1
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| 30 | #NET brd_id<2> LOC = C6 | IOSTANDARD=LVCMOS33; # P2
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| 31 | #NET brd_id<3> LOC = C7 | IOSTANDARD=LVCMOS33; # P3
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| 32 | #NET brd_id<4> LOC = C8 | IOSTANDARD=LVCMOS33; # P4
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| 33 | #NET brd_id<5> LOC = B8 | IOSTANDARD=LVCMOS33; # P5
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| 34 | #NET brd_id<6> LOC = C9 | IOSTANDARD=LVCMOS33; # P6
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| 35 | #NET brd_id<7> LOC = B9 | IOSTANDARD=LVCMOS33; # P7
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| 36 |
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| 37 |
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| 38 | # Board Addresses
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| 39 | # geographical slot address
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| 40 | #######################################################
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| 41 | #NET brd_add<0> LOC = A15 | IOSTANDARD=LVCMOS33; # ADDR0
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| 42 | #NET brd_add<1> LOC = B15 | IOSTANDARD=LVCMOS33; # ADDR1
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| 43 | #NET brd_add<2> LOC = A16 | IOSTANDARD=LVCMOS33; # ADDR2
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| 44 | #NET brd_add<3> LOC = A17 | IOSTANDARD=LVCMOS33; # ADDR3
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| 45 | #NET brd_add<4> LOC = A18 | IOSTANDARD=LVCMOS33; # ADDR4
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| 46 | #NET brd_add<5> LOC = B18 | IOSTANDARD=LVCMOS33; # ADDR5
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| 47 |
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| 48 |
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| 49 | # DAC SPI Interface
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| 50 | #######################################################
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| 51 | #NET mosi LOC = E20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #MOSI: serial data to DAC, master-out-slave-in
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| 52 | #NET sck LOC = E19 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #SCK: serial clock to DAC
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| 53 | #NET cs_ld LOC = E18 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CS: chip select or load to DAC
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| 54 | #NET clr LOC = D20 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #DAC_CRL: clear signal to DAC
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| 55 |
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| 56 |
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| 57 | # Testpoints
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| 58 | ######################################################
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| 59 | # on Connector J5
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| 60 | #NET TP_A<0> LOC = B3 | IOSTANDARD=LVCMOS33; # TP0_0
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| 61 | #NET TP_A<1> LOC = A3 | IOSTANDARD=LVCMOS33; # TP1_0
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| 62 | #NET TP_A<2> LOC = A4 | IOSTANDARD=LVCMOS33; # TP2_0
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| 63 | #NET TP_A<3> LOC = B5 | IOSTANDARD=LVCMOS33; # TP2_0
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| 64 |
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| 65 | # on Connector J6
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| 66 | #NET TP_A<4> LOC = A5 | IOSTANDARD=LVCMOS33; # TP4_0
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| 67 | #NET TP_A<5> LOC = A6 | IOSTANDARD=LVCMOS33; # TP5_0
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| 68 | #NET TP_A<6> LOC = B7 | IOSTANDARD=LVCMOS33; # TP6_0
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| 69 | #NET TP_A<7> LOC = A7 | IOSTANDARD=LVCMOS33; # TP7_0
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| 70 |
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| 71 | # on Connector J7
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| 72 | #NET TP_A<8> LOC = B11 | IOSTANDARD=LVCMOS33; # TP8_0
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| 73 | #NET TP_A<9> LOC = A12 | IOSTANDARD=LVCMOS33; # TP9_0
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| 74 | #NET TP_A<10> LOC = B12 | IOSTANDARD=LVCMOS33; # TP10_0
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| 75 | #NET TP_A<11> LOC = A14 | IOSTANDARD=LVCMOS33; # TP11_0
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| 76 |
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| 77 |
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| 78 | # Rate counter LVDS Inputs
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| 79 | ######################################################
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| 80 | # logic signal from first trigger patch
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| 81 | #NET patch_A_p LOC = Y4 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_P
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| 82 | #NET patch_A_n LOC = Y5 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS0_N
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| 83 |
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| 84 | # logic signal from second trigger patch
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| 85 | #NET patch_B_p LOC = Y6 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_P
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| 86 | #NET patch_B_n LOC = Y7 | IOSTANDARD=LVDS_33 | DIFF_TERM=No; # LVDS1_N
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| 87 |
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| 88 | # logic signal from third trigger patch
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| 89 | #NET patch_C_p LOC = Y17 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_P
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| 90 | #NET patch_C_n LOC = Y18 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS2_N
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| 91 |
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| 92 | # logic signal from fourth trigger patch
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| 93 | #NET patch_D_p LOC = Y16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_P
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| 94 | #NET patch_D_n LOC = W16 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # LVDS3_N
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| 95 |
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| 96 | #The Trigger Primitive: logic signal from n-out-of-4 circuit
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| 97 | #NET trig_prim_p LOC = Y13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P+
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| 98 | #NET trig_prim_n LOC = W13 | IOSTANDARD=LVDS_33 | DIFF_TERM=No ; # TRG_P-
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| 99 |
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| 100 |
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| 101 | # Enables
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| 102 | ######################################################
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| 103 | # Patch 0
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| 104 | NET enables_A<0> LOC = D2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_0
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| 105 | NET enables_A<1> LOC = B1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_1
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| 106 | NET enables_A<2> LOC = C2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_2
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| 107 | NET enables_A<3> LOC = D1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_3
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| 108 | NET enables_A<4> LOC = C1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_4
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| 109 | NET enables_A<5> LOC = D4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_5
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| 110 | NET enables_A<6> LOC = E1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_6
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| 111 | NET enables_A<7> LOC = D3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_7
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| 112 | NET enables_A<8> LOC = E3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; # XEN0_8
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| 113 |
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| 114 | ## Patch 1
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| 115 | NET enables_B<0> LOC = F2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_0
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| 116 | NET enables_B<1> LOC = F4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_1
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| 117 | NET enables_B<2> LOC = F3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_2
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| 118 | NET enables_B<3> LOC = F1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_3
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| 119 | NET enables_B<4> LOC = G3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_4
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| 120 | NET enables_B<5> LOC = G4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_5
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| 121 | NET enables_B<6> LOC = H2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_6
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| 122 | NET enables_B<7> LOC = H3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_7
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| 123 | NET enables_B<8> LOC = J3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN1_8
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| 124 |
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| 125 | # Patch 2
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| 126 | NET enables_C<0> LOC = N1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_0
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| 127 | NET enables_C<1> LOC = R1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_1
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| 128 | NET enables_C<2> LOC = M3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_2
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| 129 | NET enables_C<3> LOC = N2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_3
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| 130 | NET enables_C<4> LOC = P1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_4
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| 131 | NET enables_C<5> LOC = N3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_5
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| 132 | NET enables_C<6> LOC = R2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_6
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| 133 | NET enables_C<7> LOC = P3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_7
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| 134 | NET enables_C<8> LOC = T2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN2_8
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| 135 |
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| 136 | # Patch 3
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| 137 | NET enables_D<0> LOC = R3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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| 138 | NET enables_D<1> LOC = T4 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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| 139 | NET enables_D<2> LOC = T3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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| 140 | NET enables_D<3> LOC = U1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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| 141 | NET enables_D<4> LOC = U3 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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| 142 | NET enables_D<5> LOC = V1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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| 143 | NET enables_D<6> LOC = V2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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| 144 | NET enables_D<7> LOC = W1 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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| 145 | NET enables_D<8> LOC = W2 | IOSTANDARD=LVCMOS33 | SLEW = SLOW; #XEN3_0
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