source: FPGA/FTU/test_firmware/FTU_test2/FTU_test2_dac_control.vhd@ 241

Last change on this file since 241 was 241, checked in by qweitzel, 15 years ago
some add-ons for FTU_test2
File size: 4.4 KB
Line 
1----------------------------------------------------------------------------------
2-- Company: ETH Zurich, Institute for Particle Physics
3-- Engineer: P. Vogler, Q. Weitzel
4--
5-- Create Date: 05/17/2010
6-- Design Name:
7-- Module Name: FTU_test2_dac_control - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: test2 for control DAC on FTU board to set trigger thresholds
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20library IEEE;
21use IEEE.STD_LOGIC_1164.ALL;
22use IEEE.STD_LOGIC_ARITH.ALL;
23use IEEE.STD_LOGIC_UNSIGNED.ALL;
24library ftu_definitions;
25USE ftu_definitions.ftu_array_types.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31
32entity FTU_test2_dac_control is
33 port(
34 clk : IN STD_LOGIC;
35 reset : IN STD_LOGIC;
36 clr : OUT STD_LOGIC;
37 mosi : OUT STD_LOGIC;
38 sck : OUT STD_LOGIC;
39 cs_ld : out STD_LOGIC;
40 enable1 : out STD_LOGIC;
41 enable2 : out STD_LOGIC;
42 enable3 : out STD_LOGIC
43 );
44end FTU_test2_dac_control;
45
46architecture Behavioral of FTU_test2_dac_control is
47
48 component FTU_test2_spi_interface
49 port(
50 clk_50MHz : IN std_logic;
51 config_start : IN std_logic;
52 dac_array : IN dac_array_type;
53 config_ready : OUT std_logic;
54 config_started : OUT std_logic;
55 dac_cs : OUT std_logic;
56 mosi : OUT std_logic;
57 sclk : OUT std_logic;
58 miso : INOUT std_logic
59 );
60 end component;
61
62 --component FTU_test2_upcnt16
63 -- port(
64 -- full : out STD_LOGIC;
65 -- clr : in STD_LOGIC;
66 -- reset : in STD_Logic;
67 -- clk : in STD_LOGIC
68 -- );
69 --end component;
70
71 signal clk_sig : std_logic;
72 signal reset_sig : std_logic;
73
74 signal clr_sig : std_logic;
75 signal mosi_sig : std_logic := '0';
76 signal serial_clock_sig : std_logic;
77 signal dac_cs_sig : std_logic;
78
79 signal config_start_sig : std_logic := '0';
80 signal config_ready_sig : std_logic;
81 signal config_started_sig : std_logic := '0';
82 signal dac_array_sig : dac_array_type := (100,200,300,400,500);
83
84 --signal full_sig : std_logic;
85 --signal clr_wcnt_sig : std_logic;
86
87 -- Build an enumerated type for the state machine
88 type state_type is (START, WAITING, STOP);
89
90 -- Register to hold the current state
91 signal state, next_state: state_type;
92
93begin
94
95 --to be checked
96 reset_sig <= reset;
97 clk_sig <= clk;
98 mosi <= mosi_sig;
99 sck <= serial_clock_sig;
100 cs_ld <= dac_cs_sig;
101
102 -- FSM for dac control: first process
103 FSM_Registers: process(clk_sig, reset_sig)
104 begin
105 if reset_sig = '1' then
106 state <= START;
107 elsif Rising_edge(clk_sig) then
108 state <= next_state;
109 end if;
110 end process;
111
112 -- FSM for dac control: second process
113 FSM_logic: process(state, config_ready_sig)
114 begin
115 next_state <= state;
116 case state is
117 when START =>
118 config_start_sig <= '1';
119 enable1 <= '1';
120 enable2 <= '0';
121 enable3 <= '0';
122 next_state <= WAITING;
123 when WAITING =>
124 enable1 <= '0';
125 enable2 <= '1';
126 enable3 <= '0';
127 if (config_ready_sig = '1') then
128 next_state <= STOP;
129 else
130 next_state <= WAITING;
131 end if;
132 when STOP =>
133 enable1 <= '0';
134 enable2 <= '0';
135 enable3 <= '1';
136 config_start_sig <= '0';
137 end case;
138 end process;
139
140 Inst_FTU_test2_spi_interface : FTU_test2_spi_interface
141 port map(
142 clk_50MHz => clk_sig,
143 config_start => config_start_sig,
144 dac_array => dac_array_sig,
145 config_ready => config_ready_sig,
146 config_started => config_started_sig,
147 dac_cs => dac_cs_sig,
148 mosi => mosi_sig,
149 sclk => serial_clock_sig,
150 miso => open
151 );
152
153 --Inst_FTU_test2_upcnt16: FTU_test2_upcnt16
154 -- port map(
155 -- full => full_sig,
156 -- clr => clr_wcnt_sig,
157 -- reset => reset_sig,
158 -- clk => serial_clock_sig
159 -- );
160
161end Behavioral;
162
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