1 | ----------------------------------------------------------------------------------
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2 | -- Company: ETH Zurich, Institute for Particle Physics
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3 | -- Engineer: P. Vogler, Q. Weitzel
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4 | --
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5 | -- Create Date: 05/17/2010
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6 | -- Design Name:
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7 | -- Module Name: FTU_test2_dac_control - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description: test2 for control DAC on FTU board to set trigger thresholds
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | library IEEE;
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21 | use IEEE.STD_LOGIC_1164.ALL;
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22 | use IEEE.STD_LOGIC_ARITH.ALL;
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23 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
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24 | library ftu_definitions;
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25 | USE ftu_definitions.ftu_array_types.all;
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26 |
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27 | ---- Uncomment the following library declaration if instantiating
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28 | ---- any Xilinx primitives in this code.
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29 | --library UNISIM;
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30 | --use UNISIM.VComponents.all;
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31 |
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32 | entity FTU_test2_dac_control is
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33 | port(
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34 | clk : IN STD_LOGIC;
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35 | reset : IN STD_LOGIC;
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36 | clr : OUT STD_LOGIC;
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37 | mosi : OUT STD_LOGIC;
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38 | sck : OUT STD_LOGIC;
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39 | cs_ld : out STD_LOGIC;
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40 | enable1 : out STD_LOGIC;
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41 | enable2 : out STD_LOGIC;
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42 | enable3 : out STD_LOGIC
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43 | );
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44 | end FTU_test2_dac_control;
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45 |
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46 | architecture Behavioral of FTU_test2_dac_control is
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47 |
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48 | component FTU_test2_spi_interface
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49 | port(
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50 | clk_50MHz : IN std_logic;
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51 | config_start : IN std_logic;
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52 | dac_array : IN dac_array_type;
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53 | config_ready : OUT std_logic;
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54 | config_started : OUT std_logic;
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55 | dac_cs : OUT std_logic;
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56 | mosi : OUT std_logic;
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57 | sclk : OUT std_logic;
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58 | miso : INOUT std_logic
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59 | );
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60 | end component;
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61 |
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62 | --component FTU_test2_upcnt16
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63 | -- port(
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64 | -- full : out STD_LOGIC;
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65 | -- clr : in STD_LOGIC;
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66 | -- reset : in STD_Logic;
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67 | -- clk : in STD_LOGIC
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68 | -- );
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69 | --end component;
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70 |
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71 | signal clk_sig : std_logic;
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72 | signal reset_sig : std_logic;
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73 |
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74 | signal clr_sig : std_logic;
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75 | signal mosi_sig : std_logic := '0';
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76 | signal serial_clock_sig : std_logic;
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77 | signal dac_cs_sig : std_logic;
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78 |
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79 | signal config_start_sig : std_logic := '0';
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80 | signal config_ready_sig : std_logic;
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81 | signal config_started_sig : std_logic := '0';
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82 | signal dac_array_sig : dac_array_type := (100,200,300,400,500);
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83 |
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84 | --signal full_sig : std_logic;
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85 | --signal clr_wcnt_sig : std_logic;
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86 |
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87 | -- Build an enumerated type for the state machine
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88 | type state_type is (START, WAITING, STOP);
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89 |
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90 | -- Register to hold the current state
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91 | signal state, next_state: state_type;
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92 |
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93 | begin
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94 |
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95 | --to be checked
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96 | reset_sig <= reset;
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97 | clk_sig <= clk;
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98 | mosi <= mosi_sig;
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99 | sck <= serial_clock_sig;
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100 | cs_ld <= dac_cs_sig;
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101 |
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102 | -- FSM for dac control: first process
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103 | FSM_Registers: process(clk_sig, reset_sig)
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104 | begin
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105 | if reset_sig = '1' then
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106 | state <= START;
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107 | elsif Rising_edge(clk_sig) then
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108 | state <= next_state;
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109 | end if;
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110 | end process;
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111 |
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112 | -- FSM for dac control: second process
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113 | FSM_logic: process(state, config_ready_sig)
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114 | begin
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115 | next_state <= state;
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116 | case state is
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117 | when START =>
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118 | config_start_sig <= '1';
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119 | enable1 <= '1';
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120 | enable2 <= '0';
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121 | enable3 <= '0';
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122 | next_state <= WAITING;
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123 | when WAITING =>
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124 | enable1 <= '0';
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125 | enable2 <= '1';
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126 | enable3 <= '0';
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127 | if (config_ready_sig = '1') then
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128 | next_state <= STOP;
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129 | else
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130 | next_state <= WAITING;
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131 | end if;
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132 | when STOP =>
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133 | enable1 <= '0';
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134 | enable2 <= '0';
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135 | enable3 <= '1';
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136 | config_start_sig <= '0';
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137 | end case;
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138 | end process;
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139 |
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140 | Inst_FTU_test2_spi_interface : FTU_test2_spi_interface
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141 | port map(
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142 | clk_50MHz => clk_sig,
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143 | config_start => config_start_sig,
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144 | dac_array => dac_array_sig,
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145 | config_ready => config_ready_sig,
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146 | config_started => config_started_sig,
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147 | dac_cs => dac_cs_sig,
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148 | mosi => mosi_sig,
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149 | sclk => serial_clock_sig,
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150 | miso => open
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151 | );
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152 |
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153 | --Inst_FTU_test2_upcnt16: FTU_test2_upcnt16
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154 | -- port map(
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155 | -- full => full_sig,
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156 | -- clr => clr_wcnt_sig,
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157 | -- reset => reset_sig,
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158 | -- clk => serial_clock_sig
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159 | -- );
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160 |
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161 | end Behavioral;
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162 |
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